Dense electrically alterable read only memory
    1.
    发明授权
    Dense electrically alterable read only memory 失效
    密集电可更改的只读存储器

    公开(公告)号:US4375085A

    公开(公告)日:1983-02-22

    申请号:US221958

    申请日:1981-01-02

    CPC分类号: G11C16/0433

    摘要: This invention provides an improved electrically alterable read only memory system which includes a semiconductor substrate having a diffusion region therein defining one end of a channel region, a control plate, a floating plate separated from the channel region by a thin dielectric layer and disposed between the control plate and the channel region and means for transferring charge to and from the floating plate. A control gate is coupled to the channel region and is located between the diffusion region and the floating plate. The control gate may be connected to a word line and the diffusion region may be connected to a hit/sense line. The channel region is controlled by the word line and the presence or absence of charge on the floating plate. Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate. The charge transfer means includes an enhanced conduction insulator and means for applying appropriate voltages to the control plate and to the control gate to transfer charge to and from the floating plate through the enhanced conduction insulator.

    摘要翻译: 本发明提供了一种改进的电可更换只读存储器系统,其包括其中限定通道区域的一端的扩散区域的半导体衬底,控制板,通过薄介电层与沟道区分离的浮置板, 控制板和通道区域以及用于将电荷转移到浮动板和从浮动板传送电荷的装置。 控制栅极耦合到沟道区并且位于扩散区和浮置板之间。 控制栅极可以连接到字线,并且扩散区域可以连接到命中/感测线。 通道区域由字线控制,浮板上有无电荷。 因此,可以通过检测在浮动板下存储在反相电容器中的电荷的存在或不存在来从存储器的单元读取信息。 电荷转移装置包括增强的导电绝缘体和用于向控制板和控制栅极施加适当电压的装置,以通过增强的导电绝缘体将电荷转移到浮动板和从浮动板传输电荷。

    Single transistor cell for electrically-erasable programmable read-only
memory and array thereof
    2.
    发明授权
    Single transistor cell for electrically-erasable programmable read-only memory and array thereof 失效
    用于电可擦除可编程只读存储器及其阵列的单晶体管单元

    公开(公告)号:US4878101A

    公开(公告)日:1989-10-31

    申请号:US947212

    申请日:1986-12-29

    IPC分类号: G11C16/16 H01L29/788

    CPC分类号: H01L29/7885 G11C16/16

    摘要: A single transistor EEPROM cell utilizes a tunneling oxide erase mechanism in which the tunneling oxide overlies a portion of the channel region. In addition, an array of single transistor EEPROM cells having a layout which provides convenient byte-at-a-time erase and program operation is disclosed. Two bytes of the array along adjacent rows share a common source, which also forms the source of a pair of erase select transistors, one for each byte. The word lines/control gates of the two bytes form the gates of the two erase select transistors.

    摘要翻译: 单晶体管EEPROM单元利用隧道氧化物擦除机制,其中隧道氧化物覆盖在沟道区的一部分上。 此外,公开了具有提供方便的字节同时擦除和编程操作的布局的单晶体管EEPROM单元的阵列。 沿着相邻行的阵列的两个字节共享共同的源,其也形成一对擦除选择晶体管的源,每个字节一个。 两个字节的字线/控制栅极形成两个擦除选择晶体管的栅极。

    Method of making high dielectric constant insulators and capacitors
using same
    4.
    发明授权
    Method of making high dielectric constant insulators and capacitors using same 失效
    制造高介电常数绝缘体和使用其的电容器的方法

    公开(公告)号:US4432035A

    公开(公告)日:1984-02-14

    申请号:US387315

    申请日:1982-06-11

    CPC分类号: H01G2/12

    摘要: An improved method of fabricating a stable high dielectric constant and low leakage dielectric material includes oxidizing at a temperature of about 400.degree. C. or higher a layer of a transition metal-silicon alloy having 40% to 90% transition metal by atomic weight to produce a silicate or homogeneous mixture. The mixture includes an oxide of the transition metal and silicon dioxide. The alloy may be deposited on, e.g., a semiconductor or an electrically conductive layer that is oxidation resistant, and the thickness of the mixture or oxidized alloy should be within the range of 5 to 50 nanometers. By depositing an electrically conductive layer on the homogeneous mixture, a capacitor having a high dielectric, low leakage dielectric medium is provided.

    摘要翻译: 制造稳定的高介电常数和低泄漏介电材料的改进方法包括在约400℃或更高的温度下氧化具有40%至90%过渡金属的过渡金属 - 硅合金的原子量以产生 硅酸盐或均质混合物。 该混合物包括过渡金属和二氧化硅的氧化物。 合金可以沉积在例如耐氧化的半导体或导电层上,并且混合物或氧化合金的厚度应在5至50纳米的范围内。 通过在均匀混合物上沉积导电层,提供具有高电介质,低漏电介质的电容器。