公开(公告)号：US4258078A

公开(公告)日：1981-03-24

申请号：US105918

申请日：1979-12-21

申请人： George K. Celler ,  Thomas E. Seidel

发明人： George K. Celler ,  Thomas E. Seidel

IPC分类号： H01L21/263 ,  H01L21/268 ,  H01L21/321 ,  H01L21/768 ,  H01L23/525 ,  B05D3/06

CPC分类号： H01L21/2636 ,  H01L21/268 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76894 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10T29/49156

摘要： The sharp features that appear on metallization patterns defined by conventional etching processes can be eliminated by instantaneous melting with short laser pulses. Flow is minimized due to the brevity of the lifetime of the molten state but surface tension removes the sharp corners. With polysilicon metallization conductivity is also improved.

摘要翻译： 通过常规蚀刻工艺限定的金属化图案上出现的尖锐特征可以通过短激光脉冲瞬时熔化来消除。 由于熔融状态的寿命的简短，流动被最小化，而表面张力消除了尖角。 随着多晶硅金属化的传导性也得到提高。

公开(公告)号：US4581814A

公开(公告)日：1986-04-15

申请号：US681270

申请日：1984-12-13

申请人： George K. Celler ,  Pradip K. Roy ,  Donald G. Schimmel ,  Lee E. Trimble

发明人： George K. Celler ,  Pradip K. Roy ,  Donald G. Schimmel ,  Lee E. Trimble

IPC分类号： H01L21/324 ,  H01L21/762 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L21/76297 ,  H01L21/324 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/097 ,  Y10S148/122 ,  Y10S148/123 ,  Y10S438/928 ,  Y10S438/973 ,  Y10S438/977

摘要： The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas are heat treated to substantially increase their polycrystalline silicon grain size.

摘要翻译： 通过一组特定的处理步骤，显着地增强了在基片上的介电隔离器件形成的功效。 特别地，在制造氧化硅区域（例如栅极氧化物区域）之前，对大块多晶区域进行热处理以显着增加其多晶硅晶粒尺寸。

公开(公告)号：US4406709A

公开(公告)日：1983-09-27

申请号：US276932

申请日：1981-06-24

申请人： George K. Celler ,  Harry J. Leamy ,  Lee E. Trimble

发明人： George K. Celler ,  Harry J. Leamy ,  Lee E. Trimble

IPC分类号： C30B1/08 ,  H01L21/263 ,  H01L21/268 ,  H01L21/423 ,  H01L21/428

CPC分类号： H01L21/428 ,  C30B1/08 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/423 ,  Y10S117/904 ,  Y10S117/905

摘要： Crystal grain size in a material is increased by scanning the material with an appropriately directed energy beam. Short-term oscillation in the scan, and a particular temperature gradient configuration in the wake of the scan, results in growth of large-grain crystallites.

摘要翻译： 通过用适当定向的能量束扫描材料来增加材料中的晶粒尺寸。 扫描中的短期振荡以及扫描后的特定温度梯度结构导致大晶粒微晶的生长。

公开(公告)号：US20090315140A1

公开(公告)日：2009-12-24

申请号：US12548623

申请日：2009-08-27

申请人： George K. Celler

发明人： George K. Celler

IPC分类号： H01L27/12

CPC分类号： H01L21/2007 ,  H01L21/02032 ,  H01L21/67346 ,  H01L2221/68359 ,  H01L2221/68368

摘要： A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

摘要翻译： 一种用于通过提供具有第一和第二表面的晶片形成具有可回收支撑件的装置晶片的方法，至少晶片的第一表面包括适于在其上接收或形成电子器件的半导体材料，提供支撑衬底，其具有 并且提供晶片的第二表面或支撑衬底的上表面的空隙特征，其量足以使得它们之间的连接结合形成结构，其中所述结合形成在晶片和 并且适合于将晶片和支撑基板保持在一起，同时将电子器件形成或施加到晶片的第一表面，但是由于空隙特征使得该基片与晶片分离，而在该界面处的连接接合是可分离的，因此 基材可以重复使用。

公开(公告)号：US4494303A

公开(公告)日：1985-01-22

申请号：US480825

申请日：1983-03-31

申请人： George K. Celler ,  David J. Lischner ,  McDonald Robinson

发明人： George K. Celler ,  David J. Lischner ,  McDonald Robinson

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76297 ,  Y10S438/977

摘要： Structures useful for dielectrically isolated high voltage devices are produced utilizing a melting technique. In this technique a cavity is produced in a silicon wafer, the surface of the cavity is, for example, oxidized to form a dielectric material, and silicon is deposited onto the dielectric material so that it extends to a region where it is in contact with single crystal silicon, e.g., a portion of the wafer. The entire region of polycrystalline silicon is then melted. Upon termination of the melting energy, the polycrystalline silicon is converted into a thick region of dielectrically isolated single crystal silicon. This thick region is useful for the formation of high voltage devices.

摘要翻译： 使用熔化技术生产用于介电隔离的高压器件的结构。 在该技术中，在硅晶片中产生空腔，空腔的表面例如被氧化以形成介电材料，并且将硅沉积到电介质材料上，使得其延伸到与其接触的区域 单晶硅，例如晶片的一部分。 然后将多晶硅的整个区域熔化。 在熔化能量终止时，多晶硅转化为介电离子单晶硅的厚区域。 该厚区域可用于形成高压器件。

公开(公告)号：US4234358A

公开(公告)日：1980-11-18

申请号：US27274

申请日：1979-04-05

申请人： George K. Celler ,  Lionel C. Kimerling ,  Harry J. Leamy ,  John M. Poate ,  George A. Rozgonyi

发明人： George K. Celler ,  Lionel C. Kimerling ,  Harry J. Leamy ,  John M. Poate ,  George A. Rozgonyi

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/26

CPC分类号： H01L21/268 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/02689 ,  H01L21/02694 ,  Y10S117/904 ,  Y10S117/905 ,  Y10S148/09 ,  Y10S148/093

摘要： A technique isdescribed for removing defects and disorder from crystalline layers and the epitaxial regrowth of such layers. The technique involves depositing short term bursts of energy over a limited spatial region of a material thereby annealing the otherwise damaged material and causing it to epitaxially regrow. Subsequent to the short term energy deposition, similar processing is sequentially effected on adjoining and overlapping regions such that a pattern is ultimately "written". This pattern forms a continuous region of essentially single crystal material.

摘要翻译： 描述了从结晶层去除缺陷和紊乱以及这些层的外延再生长的技术。 该技术涉及在材料的有限空间区域上沉积短期的能量脉冲，从而退火另外损坏的材料并使其外延再生。 在短期能量沉积之后，在邻接和重叠的区域上顺序地进行类似的处理，使得模式最终被“写入”。 该图案形成基本单晶材料的连续区域。

公开(公告)号：US08299485B2

公开(公告)日：2012-10-30

申请号：US12810133

申请日：2008-03-19

申请人： George K. Celler

发明人： George K. Celler

IPC分类号： H01L33/00 ,  G02B6/12

CPC分类号： H01L21/8258 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12078 ,  H01L21/84 ,  H01L31/153 ,  H01L31/1852

摘要： A multilayer wafer structure containing a silicon layer that contains at least one waveguide, an insulating layer and a layer that is lattice compatible with Group III-V compounds, with the lattice compatible layer in contact with one face of the insulating layer, and the face of the insulating layer opposite the lattice compatible layer is in contact with the silicon layer. The silicon and insulating layers contain either or both of at least one continuous cavity filled with materials such as to constitute a photodetector zone, or at least one continuous cavity filled with materials such as to constitute a light source zone.

摘要翻译： 包含硅层的多层晶片结构，其包含至少一个波导，绝缘层和与III-V族化合物晶格相容的层，其中晶格相容层与绝缘层的一个面接触，并且该表面 与晶格相容层相对的绝缘层与硅层接触。 硅和绝缘层包含填充有材料的至少一个连续空腔中的一个或两个，以构成光电检测器区域，或至少一个填充有诸如构成光源区域的材料的连续空腔。

公开(公告)号：US20100295083A1

公开(公告)日：2010-11-25

申请号：US12810133

申请日：2008-03-19

申请人： George K. Celler

发明人： George K. Celler

IPC分类号： H01L33/58 ,  H01L31/0232 ,  H01L31/18 ,  H01L21/30

CPC分类号： H01L21/8258 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12078 ,  H01L21/84 ,  H01L31/153 ,  H01L31/1852

摘要： A multilayer wafer structure containing a silicon layer that contains at least one waveguide, an insulating layer and a layer that is lattice compatible with Group III-V compounds, with the lattice compatible layer in contact with one face of the insulating layer, and the face of the insulating layer opposite the lattice compatible layer is in contact with the silicon layer. The silicon and insulating layers contain either or both of at least one continuous cavity filled with materials such as to constitute a photodetector zone, or at least one continuous cavity filled with materials such as to constitute a light source zone.

摘要翻译： 包含硅层的多层晶片结构，其包含至少一个波导，绝缘层和与III-V族化合物晶格相容的层，其中晶格相容层与绝缘层的一个面接触，并且该表面 与晶格相容层相对的绝缘层与硅层接触。 硅和绝缘层包含填充有材料的至少一个连续空腔中的一个或两个，以构成光电检测器区域，或至少一个填充有诸如构成光源区域的材料的连续空腔。

公开(公告)号：US07605055B2

公开(公告)日：2009-10-20

申请号：US11142345

申请日：2005-06-02

申请人： George K. Celler

发明人： George K. Celler

IPC分类号： H01L21/46

CPC分类号： H01L21/76254

摘要： A method of manufacturing a wafer using a support substrate of a crystalline material. On the surface of the support substrate, a layer of a diamond is grown to form a first wafer in combination with the support substrate. A further substrate is bonded to the surface of the diamond layer, and a region of weakness is formed within the first wafer or the further substrate. Energy is then applied at the region of weakness to detach the structure into a first portion and a second portion.

摘要翻译： 使用结晶材料的支撑衬底制造晶片的方法。 在支撑衬底的表面上，生长金刚石层以与支撑衬底组合形成第一晶片。 另外的衬底被结合到金刚石层的表面，并且在第一晶片或另外的衬底内形成弱化区域。 然后在弱化区域施加能量以将结构分离成第一部分和第二部分。

公开(公告)号：US06388290B1

公开(公告)日：2002-05-14

申请号：US09095468

申请日：1998-06-10

申请人： George K. Celler ,  Yves Jean Chabal

发明人： George K. Celler ,  Yves Jean Chabal

IPC分类号： H01L2701

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/763

摘要： An integrated circuit comprising active and passive devices is formed in a thin slice of monocrystalline semiconductor bonded to a high resistivity polycrystalline silicon substrate. As compared with conventional integrated circuits supported on a monocrystalline substrate, circuits in monocrystalline films bonded to high resistivity polycrystalline substrates are less subject to parasitic capacitance, crosstalk and eddy currents. As compared with typical SOI wafers, the polycrystalline substrates have higher resistivity, and this resistivity is much less affected by contamination than it would be in monocrystalline substrates. Compared to silicon-on-sapphire or silicon on any other insulating material, the polycrystalline substrates are more compatible with the mechanical, thermal, and optical properties of the crystalline silicon layer.

摘要翻译： 包括有源和无源器件的集成电路形成在结合到高电阻率多晶硅衬底的单晶半导体薄片中。 与单晶衬底上支持的传统集成电路相比，结合到高电阻率多晶衬底的单晶膜中的电路较少受到寄生电容，串扰和涡流的影响。 与典型的SOI晶片相比，多晶衬底具有更高的电阻率，并且该电阻率受污染的影响要小于单晶衬底中的电阻率。 与任何其他绝缘材料上的硅 - 蓝宝石或硅相比，多晶衬底与晶体硅层的机械，热和光学性能更相容。