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    ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME
    1.
    发明申请
    ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME 有权
    包含导电结构的导体结构的电子器件和在其中的绝缘层及其形成方法

    公开(公告)号：US20130153987A1

    公开(公告)日：2013-06-20

    申请号：US13327361

    申请日：2011-12-15

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Gary H. Loechelt

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Gary H. Loechelt

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7827 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7835

    摘要： An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

    摘要翻译： 电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。 电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。 电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。 形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。

    SEMICONDUCTOR COMPONENT
    3.
    发明申请
    SEMICONDUCTOR COMPONENT 有权
    半导体元件

    公开(公告)号：US20100237409A1

    公开(公告)日：2010-09-23

    申请号：US12790987

    申请日：2010-06-01

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

    摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

    Method of forming a transistor and structure therefor
    6.
    发明授权
    Method of forming a transistor and structure therefor 有权
    形成晶体管及其结构的方法

    公开(公告)号：US09466708B2

    公开(公告)日：2016-10-11

    申请号：US13831883

    申请日：2013-03-15

    申请人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

    发明人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

    IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/70 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51

    CPC分类号： H01L29/66666 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

    摘要： In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

    摘要翻译： 在一个实施例中，半导体器件形成为包括延伸到半导体材料中的栅极结构，该半导体材料位于半导体材料的第一区域下方。 栅极结构包括导体和栅极绝缘体，栅极绝缘体具有位于栅极导体与栅极导体之下的半导体材料的第一部分之间的第一部分。 半导体材料的第一部分被配置为形成在栅极导体下面的晶体管的沟道区。 栅极结构还可以包括覆盖栅极导体并且在屏蔽导体和栅极导体之间​​具有屏蔽绝缘体的屏蔽导体。 屏蔽绝缘体还可以具有位于屏蔽导体和栅极绝缘体的第二部分之间的第二部分和覆盖屏蔽导体的第三部分。

    Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same
    8.
    发明授权
    Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same 有权
    包括沟槽内的导电结构和绝缘层的电子器件及其形成工艺

    公开(公告)号：US08679919B2

    公开(公告)日：2014-03-25

    申请号：US13327361

    申请日：2011-12-15

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Gary H. Loechelt

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Gary H. Loechelt

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7827 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7835

    摘要： An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

    摘要翻译： 电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。 电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。 电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。 形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。