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41 条记录 (耗时 0.027 秒)

    Slurryless mechanical planarization for substrate reclamation
    1.
    发明授权
    Slurryless mechanical planarization for substrate reclamation 有权
    无衬底机械平面化用于衬底回收

    公开(公告)号：US08210904B2

    公开(公告)日：2012-07-03

    申请号：US12111276

    申请日：2008-04-29

    申请人： Graham M. Bates ,  David Domina ,  James L. Hardy, Jr. ,  Eric J. White

    发明人： Graham M. Bates ,  David Domina ,  James L. Hardy, Jr. ,  Eric J. White

    IPC分类号： B24B1/00

    CPC分类号： B24B7/228 ,  H01L21/02032 ,  H01L21/02079 ,  H01L21/31053 ,  H01L21/32115

    摘要： A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

    摘要翻译： 图案化半导体衬底的图案化部分通过使用研磨垫的磨料机械平面化除去，但不使用任何浆料。 优选地，在机械平面化期间供应水以提高去除率。 材料的去除速率对于后端行业（BEOL）半导体材料中采用的普通材料来说基本上是独立的，这使得能够非选择性地去除含有金属化结构的材料。 硅的去除率低于BEOL半导体材料的去除率，能够进行自我停止的平坦化处理。

    Slurryless Mechanical Planarization for Substrate Reclamation
    2.
    发明申请
    Slurryless Mechanical Planarization for Substrate Reclamation 有权
    无碴机械平面化基板回收

    公开(公告)号：US20090270017A1

    公开(公告)日：2009-10-29

    申请号：US12111276

    申请日：2008-04-29

    申请人： Graham M. Bates ,  David Domina ,  James L. Hardy, JR. ,  Eric J. White

    发明人： Graham M. Bates ,  David Domina ,  James L. Hardy, JR. ,  Eric J. White

    IPC分类号： B24B7/20 ,  H01L21/304

    CPC分类号： B24B7/228 ,  H01L21/02032 ,  H01L21/02079 ,  H01L21/31053 ,  H01L21/32115

    摘要： A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

    摘要翻译： 图案化半导体衬底的图案化部分通过使用研磨垫的磨料机械平面化除去，但不使用任何浆料。 优选地，在机械平面化期间供应水以提高去除率。 材料的去除速率对于后端行业（BEOL）半导体材料中采用的普通材料来说基本上是独立的，这使得能够非选择性地去除含有金属化结构的材料。 硅的去除率低于BEOL半导体材料的去除率，能够进行自我停止的平坦化处理。

    CMP method
    5.
    发明授权
    CMP method 有权
    CMP方法

    公开(公告)号：US08088690B2

    公开(公告)日：2012-01-03

    申请号：US12415406

    申请日：2009-03-31

    申请人： Thomas L. McDevitt ,  Graham M. Bates ,  Eva A. Shah ,  Matthew T. Tiersch ,  Eric J. White

    发明人： Thomas L. McDevitt ,  Graham M. Bates ,  Eva A. Shah ,  Matthew T. Tiersch ,  Eric J. White

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/3212 ,  C09G1/02

    摘要： The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

    摘要翻译： 本发明是抛光衬底的方法，包括使具有至少一个包含铜的金属层的衬底与化学机械抛光组合物接触。 CMP组合物包括研磨剂，表面活性剂，氧化剂，包括聚丙烯酸或聚甲基丙烯酸的有机酸，缓蚀剂和液体载体。 金属层中的铜的一部分被磨损以抛光基底。 第二CMP组合物接触研磨的基材，第二无丙烯酸酯组合物包含研磨剂，表面活性剂，氧化剂和腐蚀抑制剂以及液体载体。 可能通过磨损去除可能在基底上形成的任何枝晶。

    CMP METHOD
    8.
    发明申请
    CMP METHOD 有权
    CMP方法

    公开(公告)号：US20100248479A1

    公开(公告)日：2010-09-30

    申请号：US12415406

    申请日：2009-03-31

    申请人： Thomas L. McDevitt ,  Graham M. Bates ,  Eva A. Shah ,  Matthew T. Tiersch ,  Eric J. White

    发明人： Thomas L. McDevitt ,  Graham M. Bates ,  Eva A. Shah ,  Matthew T. Tiersch ,  Eric J. White

    IPC分类号： H01L21/304

    CPC分类号： H01L21/3212 ,  C09G1/02

    摘要： The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

    摘要翻译： 本发明是抛光衬底的方法，包括使具有至少一个包含铜的金属层的衬底与化学机械抛光组合物接触。 CMP组合物包括研磨剂，表面活性剂，氧化剂，包括聚丙烯酸或聚甲基丙烯酸的有机酸，腐蚀抑制剂和液体载体。 金属层中的铜的一部分被磨损以抛光基底。 第二CMP组合物接触研磨的基材，第二无丙烯酸酯组合物包含研磨剂，表面活性剂，氧化剂和腐蚀抑制剂以及液体载体。 可能通过磨损去除可能在基底上形成的任何枝晶。

    Integrated BEOL thin film resistor
    10.
    发明授权
    Integrated BEOL thin film resistor 有权
    集成BEOL薄膜电阻

    公开(公告)号：US08093679B2

    公开(公告)日：2012-01-10

    申请号：US13023579

    申请日：2011-02-09

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/00 ,  H01L27/10 ,  H01L29/74 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。