利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.065 秒)

    Method to deposit conformal low temperature SiO2
    1.
    发明授权
    Method to deposit conformal low temperature SiO2 有权
    沉积保温低温SiO2的方法

    公开(公告)号：US08129289B2

    公开(公告)日：2012-03-06

    申请号：US11543515

    申请日：2006-10-05

    申请人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    发明人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    IPC分类号： H01L21/00

    CPC分类号： H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

    摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

    摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

    Method to deposit conformal low temperature SiO2
    2.
    发明申请
    Method to deposit conformal low temperature SiO2 有权
    沉积保温低温SiO2的方法

    公开(公告)号：US20080085612A1

    公开(公告)日：2008-04-10

    申请号：US11543515

    申请日：2006-10-05

    申请人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    发明人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    IPC分类号： H01L21/469

    CPC分类号： H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

    摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

    摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

    Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device
    7.
    发明申请
    Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device 审中-公开
    在制造半导体器件期间使用原子层沉积的浅沟槽隔离

    公开(公告)号：US20080179715A1

    公开(公告)日：2008-07-31

    申请号：US11699876

    申请日：2007-01-30

    申请人： Brian J. Coppa

    发明人： Brian J. Coppa

    IPC分类号： H01L23/58 ,  H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31608 ,  H01L27/11521

    摘要： A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using a high density plasma (HDP) deposition within the trench. The second dielectric provides desirable properties such as resistance to specific etches than the first dielectric, while the first dielectric fills high aspect ratio openings more easily than the second dielectric. Depositing the first dielectric results in a decreased trench aspect ratio which must be filled by the second dielectric.

    摘要翻译： 用于提供隔离材料的方法，例如用于半导体器件的沟槽隔离，包括使用在沟槽内的原子层沉积（ALD）工艺形成第一电介质，例如二氧化硅，部分蚀刻第一电介质，然后形成第二电介质 例如在沟槽内使用高密度等离子体（HDP）沉积的二氧化硅。 第二电介质提供了比第一电介质耐受特定蚀刻的所需性质，而第一电介质比第二电介质更容易地填充高纵横比开口。 沉积第一电介质导致沟槽纵横比减小，其必须由第二电介质填充。