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公开(公告)号：US20080290459A1
公开(公告)日：2008-11-27
申请号：US12182901
申请日：2008-07-30
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。
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公开(公告)号：US06949442B2
公开(公告)日：2005-09-27
申请号：US10429469
申请日：2003-05-05
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/318 , H01L27/08 , H01L21/20
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。
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公开(公告)号：US07843035B2
公开(公告)日：2010-11-30
申请号：US12182901
申请日：2008-07-30
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.
摘要翻译： MIM电容器的一个实施例包括形成在晶片上的第一绝缘层和形成在第一绝缘层内的晶片之上的第一电容器板。 MIM电容器还包括形成在第一绝缘层上的第二绝缘层，形成在第二绝缘层内的第一电容器板上的电容器电介质和形成在第二绝缘层内的电容器电介质上的第二电容器板。 在第二电容器板的第二绝缘层的上表面下方形成有凹部，在凹部形成催化活化层。
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公开(公告)号：US07436016B2
公开(公告)日：2008-10-14
申请号：US11210094
申请日：2005-08-23
IPC分类号： H01L27/108
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。
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公开(公告)号：US07268383B2
公开(公告)日：2007-09-11
申请号：US10370535
申请日：2003-02-20
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.
摘要翻译： 具有由高k电介质形成的电容器和在电介质两侧的一对互连件的半导体器件与制造这种半导体器件的方法一起提供。 互连包括通孔和金属层。
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公开(公告)号：US07615440B2
公开(公告)日：2009-11-10
申请号：US11851969
申请日：2007-09-07
IPC分类号： H01L21/8242
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.
摘要翻译： 在制造半导体器件的方法中，在间隔电介质内形成金属层。 金属层包括通过层间电介质的区域与第二金属线分离的第一金属线。 在第一金属线和第二金属线之间去除层间电介质的区域。 在去除了层间电介质的区域中的第一金属线和第二金属线之间形成高k电介质，使得由第一金属线，第二金属线和高k电介质形成电容器。
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公开(公告)号：US20070294871A1
公开(公告)日：2007-12-27
申请号：US11851969
申请日：2007-09-07
IPC分类号： H01G9/004
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.
摘要翻译： 在制造半导体器件的方法中，在间隔电介质内形成金属层。 金属层包括通过层间电介质的区域与第二金属线分离的第一金属线。 在第一金属线和第二金属线之间去除层间电介质的区域。 在去除了层间电介质的区域中的第一金属线和第二金属线之间形成高k电介质，使得由第一金属线，第二金属线和高k电介质形成电容器。
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公开(公告)号：US20050282346A1
公开(公告)日：2005-12-22
申请号：US11210094
申请日：2005-08-23
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/318 , H01L27/08 , H01L21/336 , H01L21/20
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。
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9.发明授权公开(公告)号：US06730982B2
公开(公告)日：2004-05-04
申请号：US09820900
申请日：2001-03-30
IPC分类号： H01L2900
CPC分类号： H01L21/76849 , H01L23/5258 , H01L24/05 , H01L24/45 , H01L2224/04042 , H01L2224/05647 , H01L2224/45124 , H01L2224/45147 , H01L2224/48747 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01044 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2924/00
摘要： A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad), including: a) providing a substrate having Cu wires and Cu pads embedded therein; b) selectively depositing a first metallic passivation layer on the top copper surfaces sufficient to prevent Cu oxidation and/or Cu out diffusion; c) depositing a final passivation layer; d) employing lithography and etching of the final passivation layer to cause pad opening of the fuses by exposing the passivated Cu in the bond pad area and in the fuse area; and e) causing additional passivation of open pad and open fuse areas by selective immersion deposition of Au.
摘要翻译： 制造不依赖需要附加图形化步骤（Al-via至Cu，Al-pad）的Al-引线键合焊盘的Cu FBEOL半导体器件的互连结构的工艺，包括：a）提供具有Cu线的衬底和 嵌入其中的铜焊盘; b）在顶部铜表面上选择性地沉积足以防止Cu氧化和/或Cu扩散的第一金属钝化层; c）沉积最后的钝化层; d）使用光刻和蚀刻最终钝化层 通过在接合焊盘区域和保险丝区域中暴露钝化的Cu来引起熔断器的焊盘打开; 通过Au的选择性沉积沉积导致额外的开放焊盘钝化和开放的保险丝区域。
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公开(公告)号：US06960835B2
公开(公告)日：2005-11-01
申请号：US10698057
申请日：2003-10-30
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.
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