公开(公告)号：US07410892B2

公开(公告)日：2008-08-12

申请号：US11375914

申请日：2006-03-15

申请人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

发明人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L27/10885 ,  H01L21/76831 ,  H01L21/76897 ,  H01L24/02 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

摘要翻译： 集成电路器件，例如存储器件，包括衬底，衬底上的第一绝缘层，以及设置在与衬底直接接触的第一绝缘层中的接触焊盘。 第二绝缘层设置在第一绝缘层上。 导电图案，例如镶嵌位线，设置在第二绝缘层中。 导电插塞延伸穿过第二绝缘层以接触接触焊盘并且与导电图案自对准。 绝缘膜可以分离导电图案和导电插头。 胶层可以设置在导电图案和第二绝缘层之间。 该器件还可以包括在第二绝缘层和导电图案上的第三绝缘层，并且导电插塞可延伸穿过第二和第三绝缘层。

公开(公告)号：US07045842B2

公开(公告)日：2006-05-16

申请号：US10779440

申请日：2004-02-13

申请人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

发明人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10885 ,  H01L21/76831 ,  H01L21/76897 ,  H01L24/02 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

摘要翻译： 集成电路器件，例如存储器件，包括衬底，衬底上的第一绝缘层，以及设置在与衬底直接接触的第一绝缘层中的接触焊盘。 第二绝缘层设置在第一绝缘层上。 导电图案，例如镶嵌位线，设置在第二绝缘层中。 导电插塞延伸穿过第二绝缘层以接触接触焊盘并且与导电图案自对准。 绝缘膜可以分离导电图案和导电插头。 胶层可以设置在导电图案和第二绝缘层之间。 该器件还可以包括在第二绝缘层和导电图案上的第三绝缘层，并且导电插塞可延伸穿过第二和第三绝缘层。

公开(公告)号：US20060194432A1

公开(公告)日：2006-08-31

申请号：US11375914

申请日：2006-03-15

申请人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

发明人： Hee-Sook Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

IPC分类号： H01L21/44

CPC分类号： H01L27/10885 ,  H01L21/76831 ,  H01L21/76897 ,  H01L24/02 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

摘要翻译： 集成电路器件，例如存储器件，包括衬底，衬底上的第一绝缘层，以及设置在与衬底直接接触的第一绝缘层中的接触焊盘。 第二绝缘层设置在第一绝缘层上。 导电图案，例如镶嵌位线，设置在第二绝缘层中。 导电插塞延伸穿过第二绝缘层以接触接触焊盘并且与导电图案自对准。 绝缘膜可以分离导电图案和导电插头。 胶层可以设置在导电图案和第二绝缘层之间。 该器件还可以包括在第二绝缘层和导电图案上的第三绝缘层，并且导电插塞可延伸穿过第二和第三绝缘层。

公开(公告)号：US07285493B2

公开(公告)日：2007-10-23

申请号：US10818718

申请日：2004-04-06

申请人： Sang-Bom Kang ,  Gil-Heyun Choi ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

发明人： Sang-Bom Kang ,  Gil-Heyun Choi ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Seung-Gil Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C16/16 ,  H01L21/28556 ,  H01L21/76855

摘要： Methods for depositing a metal layer on an integrated circuit device comprising providing a transition metal precursor, carrier gas and hydrogen gas to a deposition chamber such that the partial pressure of the precursor and carrier gas exceeds about 0.25 Torr and the partial pressure of hydrogen gas exceeds about 2.5 Torr are disclosed. Methods of forming a cobalt layer on an integrated circuit device are also disclosed.

摘要翻译： 一种用于在集成电路器件上沉积金属层的方法，其包括向沉积室提供过渡金属前体，载气和氢气，使得前体和载气的分压超过约0.25Torr，氢气的分压超过 公开了大约2.5托。 还公开了在集成电路器件上形成钴层的方法。

公开(公告)号：US07211506B2

公开(公告)日：2007-05-01

申请号：US10881231

申请日：2004-06-30

申请人： Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

发明人： Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

IPC分类号： H01L21/4763

CPC分类号： C23C16/56 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76855

摘要： The present invention provides methods of forming cobalt layers on a structure comprising forming a preliminary cobalt layer on a semiconductor substrate by introducing an organic metal precursor onto the semiconductor substrate and treating a surface of the preliminary cobalt layer under an atmosphere of a hydrogen-containing gas to remove impurities contained in the preliminary cobalt layer. Compositions of cobalt layers are also provided. Further provided are semiconductor devices comprising cobalt layers provided herein.

摘要翻译： 本发明提供了在包括在半导体衬底上形成初步钴层的结构上形成钴层的方法，该方法是在有机金属前体引入到半导体衬底上并在含氢气体气氛下处理预钴层的表面 以除去预备钴层中所含的杂质。 还提供了钴层的组成。 还提供了包括本文提供的钴层的半导体器件。

公开(公告)号：US20050064706A1

公开(公告)日：2005-03-24

申请号：US10924034

申请日：2004-08-23

申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

IPC分类号： H01L21/24 ,  H01L21/26 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/42 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76889

摘要： The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C≡C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

摘要翻译： 本发明提供了形成硅化钴层的方法，包括将蒸发的钴前体引入到硅衬底上以形成钴层。 蒸发的钴前体具有式Co 2（CO）6（R 1 -C = CR 2），其中R 1是H或CH 3，R 2是H，叔丁基，甲基或 乙基。 对硅衬底进行热处理，使得硅与钴反应形成硅化钴层。 还提供了用于制造包括本文所述的钴硅化物层的半导体器件的方法和这种器件。

公开(公告)号：US20070099421A1

公开(公告)日：2007-05-03

申请号：US11612225

申请日：2006-12-18

申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76889

摘要： The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C≡C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

摘要翻译： 本发明提供了形成硅化钴层的方法，包括将蒸发的钴前体引入到硅衬底上以形成钴层。 蒸发的钴前体具有下式：CO 2 - （CO）6（R 1 - C≡CR2） 其中R 1是H或CH 3，R 2是H，叔丁基，甲基或乙基。 对硅衬底进行热处理，使得硅与钴反应形成硅化钴层。 还提供了用于制造包括本文所述的钴硅化物层的半导体器件的方法和这种器件。

公开(公告)号：US07172967B2

公开(公告)日：2007-02-06

申请号：US10924034

申请日：2004-08-23

申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Woong-Hee Sohn ,  Jong-Ho Yun ,  Kwang-Jin Moon

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76889

摘要： The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C≡C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

摘要翻译： 本发明提供了形成硅化钴层的方法，包括将蒸发的钴前体引入到硅衬底上以形成钴层。 蒸发的钴前体具有下式：CO 2 - （CO）6（R 1 - C≡CR2） 其中R 1是H或CH 3，R 2是H，叔丁基，甲基或乙基。 对硅衬底进行热处理，使得硅与钴反应形成硅化钴层。 还提供了用于制造包括本文所述的钴硅化物层的半导体器件的方法和这种器件。

公开(公告)号：US20050014365A1

公开(公告)日：2005-01-20

申请号：US10881231

申请日：2004-06-30

申请人： Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

发明人： Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

IPC分类号： H01L21/24 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768

CPC分类号： C23C16/56 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76855

摘要： The present invention provides methods of forming cobalt layers on a structure comprising forming a preliminary cobalt layer on a semiconductor substrate by introducing an organic metal precursor onto the semiconductor substrate and treating a surface of the preliminary cobalt layer under an atmosphere of a hydrogen-containing gas to remove impurities contained in the preliminary cobalt layer. Compositions of cobalt layers are also provided. Further provided are semiconductor devices comprising cobalt layers provided herein.

摘要翻译： 本发明提供了在包括在半导体衬底上形成初步钴层的结构上形成钴层的方法，该方法是在有机金属前体引入到半导体衬底上并在含氢气体气氛下处理预钴层的表面 以除去预备钴层中所含的杂质。 还提供了钴层的组成。 还提供了包括本文提供的钴层的半导体器件。

公开(公告)号：US20080211038A1

公开(公告)日：2008-09-04

申请号：US11965420

申请日：2007-12-27

申请人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hyun-Su Kim ,  Eun-Ok Lee

发明人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hyun-Su Kim ,  Eun-Ok Lee

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/28097 ,  H01L29/4975 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。 初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。 该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物 并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。 金属硅化物层和金属导电图案构成栅电极。