公开(公告)号：US08860225B2

公开(公告)日：2014-10-14

申请号：US13271878

申请日：2011-10-12

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/316 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US20120119389A1

公开(公告)日：2012-05-17

申请号：US12946138

申请日：2010-11-15

申请人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

发明人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.

摘要翻译： 一种方法包括构造半导体衬底以产生数量的半导体芯片。 每个半导体芯片包括第一主面和多个侧面。 在第一主面和侧面之间的过渡处形成有凹陷。

公开(公告)号：US08013364B2

公开(公告)日：2011-09-06

申请号：US12579807

申请日：2009-10-15

申请人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

发明人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

IPC分类号： H01L23/52

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

摘要翻译： 公开了一种在互连之间具有气隙的结构。 第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。 导电线形成在第一和第二绝缘层中。 处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。 第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。 工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是 不是第一个地区。

公开(公告)号：US07871902B2

公开(公告)日：2011-01-18

申请号：US12030435

申请日：2008-02-13

申请人： Erdem Kaltalioglu ,  Hermann Wendt

发明人： Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/31116

摘要： Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

摘要翻译： 公开了形成裂纹停止沟槽的结构和方法。 该方法包括形成设置在衬底的单元区域中的有源区，由切割通道分离的单元区域，以及在衬底上形成后端（BEOL）层，在单元区域和切割通道上形成BEOL层。 然后通过蚀刻围绕单元区域的一部分BEOL层，形成围绕单元区域的裂纹停止沟槽。 晶片沿着切割通道切割。

公开(公告)号：US07629225B2

公开(公告)日：2009-12-08

申请号：US11151134

申请日：2005-06-13

申请人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

发明人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

IPC分类号： H01L21/76

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

摘要翻译： 公开了在集成电路的互连和其结构之间形成气隙的方法。 第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。 导电线形成在第一和第二绝缘层中。 处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。 第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。 工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是 不是第一个地区。

公开(公告)号：US20090011556A9

公开(公告)日：2009-01-08

申请号：US09948010

申请日：2001-09-05

申请人： Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

发明人： Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

IPC分类号： H01L21/00 ,  H01L21/8242

CPC分类号： H01L28/60 ,  H01L21/02071 ,  H01L21/32136 ,  H01L28/55

摘要： A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

申请人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

发明人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US5347696A

公开(公告)日：1994-09-20

申请号：US164719

申请日：1993-12-10

申请人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

发明人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

IPC分类号： C23F4/00 ,  H01G4/30 ,  H01L21/822 ,  H01L27/04 ,  H01G4/10

CPC分类号： H01G4/306 ,  Y10T29/435

摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).

摘要翻译： 为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层 （2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。 在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在 所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

公开(公告)号：US20130277797A1

公开(公告)日：2013-10-24

申请号：US13452669

申请日：2012-04-20

申请人： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

发明人： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC分类号： H01L21/76 ,  H01L27/04

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

摘要： A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

公开(公告)号：US07723818B2

公开(公告)日：2010-05-25

申请号：US11805232

申请日：2007-05-22

申请人： Armin Tilke ,  Frank Huebinger ,  Hermann Wendt

发明人： Armin Tilke ,  Frank Huebinger ,  Hermann Wendt

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76232

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。 沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。 第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。 第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。