公开(公告)号：US20060081188A1

公开(公告)日：2006-04-20

申请号：US11107819

申请日：2005-04-18

申请人： Hideki Komori ,  Masao Sumiyoshi ,  Toshio Tanaka ,  Miharu Kawashima

发明人： Hideki Komori ,  Masao Sumiyoshi ,  Toshio Tanaka ,  Miharu Kawashima

IPC分类号： C23C16/00

CPC分类号： C23C14/564 ,  C23C14/26 ,  C23C14/30

摘要： A vacuum deposition system comprises a vacuum vessel, an evaporation source holder provided in the vacuum vessel for holding an evaporation substance and a holding jig provided in the vacuum vessel for holding a substrate facing the evaporation source. An adhesion-prevention member is provided at outer peripheries of the evaporation source and the holding jig along an inner wall of the vacuum vessel across a region from a position facing a lateral part of the evaporation source holder to a position facing a lateral part of the holding jig. The adhesion-prevention member is spaced apart from the inner wall of the vacuum vessel. The adhesion-prevention member includes members slanted diagonally downward from the central part side toward the inner wall. Thereby, the adhesion-prevention member prevents an evaporant from the evaporation source from adhering to the inner wall of the vacuum vessel.

摘要翻译： 真空沉积系统包括真空容器，设置在用于保持蒸发物质的真空容器中的蒸发源保持器和设置在真空容器中用于保持面向蒸发源的基板的保持夹具。 在蒸发源和保持夹具的外周沿着真空容器的内壁横跨从面对蒸发源保持器的侧部的位置到面向该蒸发源的侧部的位置的区域设置防粘附构件 夹具 防粘附构件与真空容器的内壁间隔开。 防粘接构件包括从中心部分侧向内壁倾斜向下倾斜的构件。 因此，防粘接部件防止蒸发源蒸发剂粘附到真空容器的内壁。

公开(公告)号：US09390995B2

公开(公告)日：2016-07-12

申请号：US14370803

申请日：2012-07-25

申请人： Kei Yamamoto ,  Kazuhiro Tada ,  Hideki Komori ,  Toru Kimura ,  Masaki Goto ,  Hiroyuki Yoshihara

发明人： Kei Yamamoto ,  Kazuhiro Tada ,  Hideki Komori ,  Toru Kimura ,  Masaki Goto ,  Hiroyuki Yoshihara

IPC分类号： H01L23/367 ,  H01L23/34 ,  B23P15/26 ,  H01L23/433 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.

摘要翻译： 目的在于提供一种鳍状集成型半导体器件及其制造方法，其具有简单的结构和良好的散热特性。 半导体器件包括：在第一主面上形成有以直立状态排列的翅片的基板; 绝缘层，形成在所述基板的第二主面上，所述第二主面与所述基板的所述第一主面相对; 固定到所述绝缘层的电路图案; 以及连接到电路图案的半导体元件。 翅片形成有沿翅片的厚度方向穿过的狭缝。

公开(公告)号：US06579769B2

公开(公告)日：2003-06-17

申请号：US09726384

申请日：2000-12-01

申请人： Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

发明人： Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

IPC分类号： H01L21336

CPC分类号： H01L21/76221

摘要： In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the first window is enhanced. Accordingly, generation of projection on bird's beak of a selective oxide film can be prevented in a semiconductor device manufacturing method including a step of growing a local oxidation of silicon film.

摘要翻译： 在制造半导体器件的方法中，包括在半导体衬底的表面上形成防氧化层的步骤，在氧化防止层中形成第一窗口，将半导体衬底放置在第一气氛中，其中氧气 气体和第一量的氯气通过第一温度被供应，然后在第一温度下加热半导体衬底，使得通过热氧化从第一窗口暴露的半导体衬底的表面来生长第一选择性氧化物膜，形成第二 通过图案化氧化防止层，并将半导体衬底放置在第二气氛中，在第二气氛中，将氧气和大于第一量的第二量的氯气供给到第二气氛中，然后在 第二温度使得形成第二选择性氧化物膜，并且形成第一选择性氧化物膜的厚度 增强了形成在第一窗口下方的氧化膜。 因此，在包括生长硅膜的局部氧化的步骤的半导体器件制造方法中，可以防止在选择性氧化物膜的鸟嘴上产生投影。

公开(公告)号：US06242305B1

公开(公告)日：2001-06-05

申请号：US09427404

申请日：1999-10-25

申请人： David K. Foote ,  Hideki Komori ,  Bharath Rangarajan ,  Fei Wang

发明人： David K. Foote ,  Hideki Komori ,  Bharath Rangarajan ,  Fei Wang

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure overlying the semiconductor substrate. Thereafter, a hard mask layer is formed to overlie ONO structure, the hard mask layer having an upper surface. To form a trench for the buried bit-line, an etch process is performed on the ONO structure. Thereafter, silicon dioxide is deposited to fill the trench. To control a thickness of the deposited silicon dioxide, a chemical-mechanical-polishing process is performed to planarize the silicon dioxide and form a planar surface continuous with the upper surface of the hard mask layer. Finally, the hard mask layer is removed and the remaining silicon dioxide forms a uniform bit-line oxide layer.

摘要翻译： 制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的ONO结构。 此后，形成硬掩模层以覆盖ONO结构，硬掩模层具有上表面。 为了形成掩埋位线的沟槽，对ONO结构进行蚀刻处理。 此后，沉积二氧化硅以填充沟槽。 为了控制沉积的二氧化硅的厚度，进行化学机械抛光工艺以使二氧化硅平坦化并形成与硬掩模层的上表面连续的平面。 最后，去除硬掩模层，剩余的二氧化硅形成均匀的位线氧化物层。

公开(公告)号：US5770304A

公开(公告)日：1998-06-23

申请号：US500836

申请日：1995-07-11

申请人： Koji Nakamura ,  Hideki Komori ,  Mitsuyuki Oda ,  Kazunori Kanda

发明人： Koji Nakamura ,  Hideki Komori ,  Mitsuyuki Oda ,  Kazunori Kanda

IPC分类号： H01Q17/00 ,  B32B5/16

CPC分类号： H01Q17/00 ,  H01Q17/004 ,  Y10S428/90 ,  Y10T428/256 ,  Y10T428/257 ,  Y10T428/258 ,  Y10T428/259 ,  Y10T428/26

摘要： The present invention provides a thin wide bandwidth electromagnetic wave absorbing material capable of absorbing electromagnetic waves in both the semi-microwave band and the semi-millimeter and millimeter wave band. The present electromagnetic wave absorbing material comprises: a first layer composed of a conductive material; a second layer comprising a particle of a metal oxide magnetic material and a matrix of a binder, being applied on the first layer; and a third layer comprising a particle of a metal magnetic material and a matrix of a binder, being applied on the second layer.

摘要翻译： 本发明提供能够吸收半微波带和半毫米和毫米波段中的电磁波的薄宽带宽电磁波吸收材料。 本电磁波吸收材料包括：由导电材料构成的第一层; 第二层，其包含金属氧化物磁性材料的颗粒和粘合剂的基体，施加在第一层上; 以及第三层，其包含金属磁性材料的颗粒和粘合剂的基体，施加在第二层上。

公开(公告)号：US20070117303A1

公开(公告)日：2007-05-24

申请号：US11656438

申请日：2007-01-23

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/115 ,  H01L27/11568 ,  Y10S257/90

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

摘要翻译： 漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b） 其浓度高于轻掺杂浅杂质区（7a）的浓度。 轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的提高。 漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

公开(公告)号：US06713809B1

公开(公告)日：2004-03-30

申请号：US09809969

申请日：2001-03-16

申请人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

发明人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。

公开(公告)号：US06573140B1

公开(公告)日：2003-06-03

申请号：US09810155

申请日：2001-03-16

申请人： Jusuke Ogura ,  Kiyoshi Izumi ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

发明人： Jusuke Ogura ,  Kiyoshi Izumi ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。 还公开了用于制造根据本发明的存储器件的工艺。

公开(公告)号：US06187640B1

公开(公告)日：2001-02-13

申请号：US09193252

申请日：1998-11-17

申请人： Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

发明人： Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

IPC分类号： H01L21336

CPC分类号： H01L21/76221

摘要： In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the first window is enhanced. Accordingly, generation of projection on bird's beak of a selective oxide film can be prevented in a semiconductor device manufacturing method including a step of growing a local oxidation of silicon film.

摘要翻译： 在制造半导体器件的方法中，包括在半导体衬底的表面上形成氧化防止层的步骤，在氧化防止层中形成第一窗口，将半导体衬底放置在第一气氛中，其中氧气 并且在第一温度下通过第一量的氯气供应第一量的氯气，然后在第一温度下加热第一选择性氧化物膜，以便通过热氧化从第一窗口露出的半导体衬底的表面生长第一选择性氧化物膜，形成第二窗口 通过图案化氧化防止层，并且将半导体衬底放置在第二气氛中，在第二气氛中，将氧气和大于第一量的第二量的氯气供给到第二气氛中，然后再次加热半导体衬底 温度使得形成第二选择性氧化物膜，并且第一选择性氧化物膜的厚度 在第一窗口下方形成的底片增强。 因此，在包括生长硅膜的局部氧化的步骤的半导体器件制造方法中，可以防止在选择性氧化物膜的鸟嘴上产生投影。

公开(公告)号：US20140367702A1

公开(公告)日：2014-12-18

申请号：US14370803

申请日：2012-07-25

申请人： Kei Yamamoto ,  Kazuhiro Tada ,  Hideki Komori ,  Toru Kimura ,  Masaki Goto ,  Hiroyuki Yoshihara

发明人： Kei Yamamoto ,  Kazuhiro Tada ,  Hideki Komori ,  Toru Kimura ,  Masaki Goto ,  Hiroyuki Yoshihara

IPC分类号： H01L23/367 ,  H01L29/20 ,  H01L21/56 ,  H01L29/16 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.

摘要翻译： 目的在于提供一种鳍状集成型半导体器件及其制造方法，其具有简单的结构和良好的散热特性。 半导体器件包括：在第一主面上形成有以直立状态排列的翅片的基板; 绝缘层，形成在所述基板的第二主面上，所述第二主面与所述基板的所述第一主面相对; 固定到所述绝缘层的电路图案; 以及连接到电路图案的半导体元件。 翅片形成有沿翅片的厚度方向穿过的狭缝。