公开(公告)号：US06326284B1

公开(公告)日：2001-12-04

申请号：US08610488

申请日：1996-03-04

申请人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

发明人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

IPC分类号： H01L2176

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/76202 ,  H01L29/518

摘要： A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.

摘要翻译： 通过在基板上形成氧化膜而制造的半导体装置，在惰性气氛中，在800℃以上的温度下进行氧化膜的热处理，接着是用于形成晶体管的常规步骤，由于 松弛在氧化膜或衬底表面产生的应力。

公开(公告)号：US07084477B2

公开(公告)日：2006-08-01

申请号：US10600771

申请日：2003-06-23

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US20060214254A1

公开(公告)日：2006-09-28

申请号：US11443226

申请日：2006-05-31

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US06559037B2

公开(公告)日：2003-05-06

申请号：US09809046

申请日：2001-03-16

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US06204155B1

公开(公告)日：2001-03-20

申请号：US09597985

申请日：2000-06-19

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

公开(公告)号：US06187100B1

公开(公告)日：2001-02-13

申请号：US09413890

申请日：1999-10-07

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： C23C1600

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US6080611A

公开(公告)日：2000-06-27

申请号：US880445

申请日：1997-06-24

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L21/8247 ,  C23C16/24 ,  C23C16/44 ,  C23C16/455 ,  C23C16/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/04 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L31/18 ,  H01L21/8238

CPC分类号： C23C16/45561 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

公开(公告)号：US5670793A

公开(公告)日：1997-09-23

申请号：US527942

申请日：1995-09-14

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L21/8247 ,  C23C16/24 ,  C23C16/44 ,  C23C16/455 ,  C23C16/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/04 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L31/18

CPC分类号： C23C16/45561 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US07244643B2

公开(公告)日：2007-07-17

申请号：US10496766

申请日：2002-11-21

申请人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

IPC分类号： H01L21/8238

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

摘要翻译： 本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。 实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜 到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。 根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

公开(公告)号：US06982465B2

公开(公告)日：2006-01-03

申请号：US10433786

申请日：2001-12-06

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092

摘要： The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

摘要翻译： 本发明提供一种包括n沟道场效应晶体管和p沟道场效应晶体管的半导体器件，其全部具有优良的漏极电流特性。 在包括n沟道场效应晶体管10和p沟道场效应晶体管30的半导体器件中，覆盖n沟道场效应晶体管10的栅电极15的应力控制膜19经受主要由拉伸应力 。 与n沟道场效应晶体管10的膜19相比，覆盖p沟道场效应晶体管30的栅电极15的应力控制膜39主要由压缩应力引起的膜应力。 因此，预期在n沟道场效应晶体管和p沟道场效应晶体管两者中都会改善漏极电流。 因此，通常可以提高特性。