公开(公告)号：US09053401B2

公开(公告)日：2015-06-09

申请号：US11631688

申请日：2005-07-28

Applicant: Ryosuke Watanabe ,  Naoto Kusumoto ,  Osamu Nakamura

Inventor： Ryosuke Watanabe ,  Naoto Kusumoto ,  Osamu Nakamura

IPC: H01L27/10 ,  B29C65/00 ,  B32B37/00 ,  G06K19/077 ,  B32B37/22 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L27/1266 ,  B32B37/0053 ,  B32B37/226 ,  B32B2425/00 ,  G06K19/077 ,  G06K19/07718 ,  H01L24/86 ,  H01L27/1214 ,  H01L2224/7965 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/00

Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.

Abstract translation: 薄膜集成电路从基板剥离，并且剥离的薄膜集成电路被有效地密封以提高制造成品率。 本发明提供了一种层叠体系，其包括用于输送设置有多个薄膜集成电路的基板的输送机构; 第一剥离装置，用于将薄膜集成电路的第一表面接合到第一片状部件，以从基板剥离薄膜集成电路; 第二剥离装置，用于将薄膜集成电路的第二表面接合到第二片状部件，以将薄膜集成电路从第一片状部件剥离; 以及密封装置，用于将所述薄膜集成电路插入所述第二片状部件和第三片状部件之间，以与所述第二片状部件和所述第三片状部件密封所述薄膜集成电路。

公开(公告)号：US08698156B2

公开(公告)日：2014-04-15

申请号：US12403988

申请日：2009-03-13

Applicant: Ryosuke Watanabe ,  Hidekazu Takahashi ,  Takuya Tsurume

Inventor： Ryosuke Watanabe ,  Hidekazu Takahashi ,  Takuya Tsurume

IPC: H01L29/12 ,  H01L29/786 ,  H01L23/31

CPC classification number: H01L21/56 ,  B32B37/20 ,  B32B2305/342 ,  B42D25/45 ,  B42D2033/46 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67126 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6835 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68318 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2924/0002 ,  Y10T156/1089 ,  Y10T156/1093 ,  Y10T156/1712 ,  H01L2924/00

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract translation: 本发明的目的是提高密封薄膜集成电路的生产效率并防止损坏和断裂。 此外，本发明的另一个目的是防止薄膜集成电路在运输中受损，并且使得更容易处理薄膜集成电路。 本发明提供了一种层压系统，其中辊子用于供应用于密封的基板，接收IC芯片，分离和密封。 通过旋转辊可以连续地进行多个薄膜集成电路的分离，密封和接收; 从而可以极大地提高生产效率。 此外，由于使用了彼此相对的一对辊，所以能够容易地密封薄膜集成电路。

公开(公告)号：US08481377B2

公开(公告)日：2013-07-09

申请号：US13026518

申请日：2011-02-14

Applicant: Kengo Akimoto ,  Ryosuke Watanabe ,  Masashi Tsubuku ,  Shunpei Yamazaki

Inventor： Kengo Akimoto ,  Ryosuke Watanabe ,  Masashi Tsubuku ,  Shunpei Yamazaki

IPC: H01L21/338

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618

Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.

Abstract translation: 本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。 栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。 通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。 因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

公开(公告)号：US20110287591A1

公开(公告)日：2011-11-24

申请号：US13110314

申请日：2011-05-18

Applicant: Shunpei YAMAZAKI ,  Ryosuke WATANABE ,  Suzunosuke HIRAISHI ,  Junichiro SAKATA

Inventor： Shunpei YAMAZAKI ,  Ryosuke WATANABE ,  Suzunosuke HIRAISHI ,  Junichiro SAKATA

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/477 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.

Abstract translation: 目的在于提供一种具有稳定的电气特性和高可靠性的氧化物半导体的半导体装置。 在包括氧化物半导体层的底栅晶体管的制造工艺中，在氧化物气氛中进行热处理，在真空中进行热处理，依次进行氧化物半导体层的脱水或脱氢。 此外，与热处理同时进行具有短波长的光的照射，由此促进氢，OH等的消除。 包括通过这种热处理进行脱水或脱氢处理的氧化物半导体层的晶体管具有改善的稳定性，从而抑制了由于光照射或偏压温度应力（BT）测试而导致的晶体管的电特性的变化。

公开(公告)号：US20110068335A1

公开(公告)日：2011-03-24

申请号：US12887646

申请日：2010-09-22

Applicant: Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L29/78696 ,  H01L21/2636 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/12 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Abstract translation: 本发明的目的是提供具有良好电气特性的高度可靠的半导体器件以及包括半导体器件作为开关元件的显示器件。 在包括氧化物半导体层的晶体管中，设置在氧化物半导体层的至少一个表面侧上的针状晶体在垂直于该表面的c轴方向上生长，并且包括平行于该表面的ab平面，以及除了 针状晶体组是无定形区域或非晶态和微晶体混合的区域。 因此，可以形成具有良好电特性的高可靠性半导体器件。

公开(公告)号：US07863154B2

公开(公告)日：2011-01-04

申请号：US11989328

申请日：2006-07-21

Applicant: Shunpei Yamazaki ,  Ryosuke Watanabe ,  Jun Koyama

Inventor： Shunpei Yamazaki ,  Ryosuke Watanabe ,  Jun Koyama

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/00 ,  G06K19/077 ,  G06K19/07

CPC classification number: H01L21/6835 ,  H01L23/552 ,  H01L23/60 ,  H01L24/75 ,  H01L24/83 ,  H01L27/1248 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.

Abstract translation: 提供了一种半导体器件的制造方法，其包括在第一衬底上形成晶体管的工艺; 在晶体管上形成第一绝缘层的工艺; 形成与晶体管的源极或漏极连接的第一导电层的工序; 其中设置有第二绝缘层的第二基板被布置成使得第一绝缘层附接到第二绝缘层的工艺; 第二绝缘层与第二基板分离的工序; 并且其中设置有用作天线的第二导电层的第三基板被布置成使得第一导电层电连接到第二导电层的工艺。

公开(公告)号：US07521383B2

公开(公告)日：2009-04-21

申请号：US11425559

申请日：2006-06-21

Applicant: Masafumi Morisue ,  Ryosuke Watanabe ,  Junya Maruyama ,  Daiki Yamada

Inventor： Masafumi Morisue ,  Ryosuke Watanabe ,  Junya Maruyama ,  Daiki Yamada

IPC: H01L21/00

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/13 ,  H01L31/18 ,  Y10S438/94

Abstract: A first layer (an insulating layer), a second layer (a metal layer), and a third layer (an insulating layer) are formed over a substrate. Then, a fourth layer including a semiconductor element is formed over the third layer. After applying an organic resin film covering the fourth layer, laser light is irradiated to sections of a rear surface side of the substrate. By irradiating the second layer with laser light, the state of being covered with the organic resin film can be maintained at the same time as forming a space under the organic resin film by ablating (alternatively, evaporating or breaking down) an irradiated region of the second layer, to cause a lift in the film in a periphery thereof.

Abstract translation: 在基板上形成第一层（绝缘层），第二层（金属层）和第三层（绝缘层）。 然后，在第三层上形成包括半导体元件的第四层。 在涂覆覆盖第四层的有机树脂膜之后，激光照射到基板的后表面侧的部分。 通过用激光照射第二层，可以在与有机树脂膜之间形成空间的同时通过烧蚀（或者，蒸发或分解）有机树脂膜的照射区域同时保持有机树脂膜被覆盖的状态。 第二层，以在其周围引起膜的提升。

公开(公告)号：US20070045805A1

公开(公告)日：2007-03-01

申请号：US11491037

申请日：2006-07-24

Applicant: Ryosuke Watanabe ,  Daiki Yamada

Inventor： Ryosuke Watanabe ,  Daiki Yamada

IPC: H01L23/02

CPC classification number: G06K19/07749 ,  H01L23/49855 ,  H01L27/12 ,  H01L27/1266 ,  H01L27/1292 ,  H01L27/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device which is excellent in chemical and physical strength and circumstance resistance is provided. A first stacked film including a first base material and a first adhesive layer is adhered so as to cover one surface of a stacked body including an integrated circuit, the stacked body is sealed by adhering a second stacked film including a second base material and a second adhesive layer so as to cover the other surface of the stacked body, and the first stacked film and the second stacked film are cut. Then, a side surface of the first stacked film and the second stacked film, which is exposed by the cutting, is irradiated with laser light.

Abstract translation: 提供了具有优异的化学和物理强度和环境阻力的半导体器件。 将包括第一基材和第一粘合剂层的第一叠层膜粘合以覆盖包括集成电路的层叠体的一个表面，通过将包括第二基材和第二基材的第二叠层膜 粘合剂层以覆盖层叠体的另一面，并且切割第一层叠膜和第二层叠膜。 然后，用激光照射通过切割曝光的第一层叠膜和第二层叠膜的侧面。

公开(公告)号：US20060011288A1

公开(公告)日：2006-01-19

申请号：US11168353

申请日：2005-06-29

Applicant: Ryosuke Watanabe ,  Hidekazu Takahashi ,  Takuya Tsurume ,  Yasuyuki Arai ,  Yasuko Watanabe ,  Miyuki Higuchi

Inventor： Ryosuke Watanabe ,  Hidekazu Takahashi ,  Takuya Tsurume ,  Yasuyuki Arai ,  Yasuko Watanabe ,  Miyuki Higuchi

IPC: B32B37/00 ,  B29C65/00

CPC classification number: H01L21/56 ,  B32B37/153 ,  B32B37/226 ,  B32B2305/342 ,  B32B2519/02 ,  G06K19/07718 ,  G06K19/07749 ,  H01L21/67132 ,  H01L2924/0002 ,  Y10T29/41 ,  Y10T156/1095 ,  Y10T156/1734 ,  H01L2924/00

Abstract: The invention provides a laminating system in which one of second and third substrates for sealing a thin film integrated circuit is supplied to a first substrate having the plurality of thin film integrated circuit while being extruded in a heated and melted state, and further rollers are used for supplying the other substrate, receiving IC chips, separating, and sealing. Processes of separating the thin film integrated circuits provided over the first substrate, sealing the separated thin film integrated circuits, and receiving the sealed thin film integrated circuits can be continuously carried out by rotating the rollers. Thus, the production efficiency can be extremely improved.

公开(公告)号：US08625085B2

公开(公告)日：2014-01-07

申请号：US13407943

申请日：2012-02-29

Applicant: Ryosuke Watanabe ,  Masashi Tsubuku ,  Takayuki Inoue

Inventor： Ryosuke Watanabe ,  Masashi Tsubuku ,  Takayuki Inoue

IPC: G01N21/00

CPC classification number: H01L22/14 ,  H01L22/12

Abstract: Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.

Abstract translation: 即使在具有低光响应的样品（例如宽带隙半导体）的情况下，也提供了能够进行高度精确的CPM测量的测量方法。 当进行CPM测量时，通过向除了两个电极之外的样品中提供的第三电极施加正偏置电压，立即除去通过光照射出具有低光响应的样品（例如宽带隙半导体）产生的光激发载流子 用于测量。 当除去光激发载体时，即使在样品表现出较低的光响应的情况下，光电流值的可控性得到改善，也可以精确地进行CPM测量。