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    Computer system including an interrupt controller
    1.
    发明授权
    Computer system including an interrupt controller 有权
    计算机系统包括一个中断控制器

    公开(公告)号：US08589612B2

    公开(公告)日：2013-11-19

    申请号：US13106788

    申请日：2011-05-12

    申请人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    发明人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

    摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

    摘要翻译： 提供一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

    COMPUTER SYSTEM
    2.
    发明申请
    COMPUTER SYSTEM 有权
    电脑系统

    公开(公告)号：US20110283033A1

    公开(公告)日：2011-11-17

    申请号：US13106788

    申请日：2011-05-12

    申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    IPC分类号： G06F13/24 ,  G06F13/26

    CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

    摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

    摘要翻译： 提供了一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

    Communications system, and informaton processing device and control device incorporating said communications system
    4.
    发明申请
    Communications system, and informaton processing device and control device incorporating said communications system 失效
    通信系统，以及包含所述通信系统的信息处理装置和控制装置

    公开(公告)号：US20060036704A1

    公开(公告)日：2006-02-16

    申请号：US10980837

    申请日：2004-11-04

    申请人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

    发明人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

    IPC分类号： G06F15/16

    CPC分类号： G06F13/4217

    摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.

    摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。

    Communications system, and information processing device and control device incorporating said communications system
    5.
    发明授权
    Communications system, and information processing device and control device incorporating said communications system 失效
    通信系统，以及包含所述通信系统的信息处理设备和控制设备

    公开(公告)号：US07765269B2

    公开(公告)日：2010-07-27

    申请号：US10980837

    申请日：2004-11-04

    申请人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

    发明人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

    IPC分类号： G06F15/16

    CPC分类号： G06F13/4217

    摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.

    摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。

    A/D converter and a microcontroller including the same
    6.
    发明授权
    A/D converter and a microcontroller including the same 有权
    A / D转换器和包含它的微控制器

    公开(公告)号：US07245248B2

    公开(公告)日：2007-07-17

    申请号：US10912542

    申请日：2004-08-06

    申请人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

    发明人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

    IPC分类号： H03M1/12

    CPC分类号： H03M1/1225

    摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.

    摘要翻译： 在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加 加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。 每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

    MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT
    7.
    发明申请
    MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT 有权
    具有检测加工结果的多核微型计算机

    公开(公告)号：US20100131741A1

    公开(公告)日：2010-05-27

    申请号：US12610422

    申请日：2009-11-02

    申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F9/38

    CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

    摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

    摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

    Multi-core microcontroller having comparator for checking processing result
    8.
    发明授权
    Multi-core microcontroller having comparator for checking processing result 有权
    具有用于检查处理结果的比较器的多核微控制器

    公开(公告)号：US08433955B2

    公开(公告)日：2013-04-30

    申请号：US12610422

    申请日：2009-11-02

    申请人： Hiromichi Yamada ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    发明人： Hiromichi Yamada ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

    摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

    摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步执行相同的处理时，获得相同处理结果的定时也是不同的，因此压缩机进行压缩，因此可以容易地将它们的处理结果进行比较。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。