公开(公告)号：US20060120828A1

公开(公告)日：2006-06-08

申请号：US11234229

申请日：2005-09-26

申请人： Hirotaka Kato

发明人： Hirotaka Kato

IPC分类号： B42B9/00

CPC分类号： B42D3/002

摘要： To provide a book binding kit easy for a user to fabricate an original book, it includes one set composed of a paper having a printing surface and an adhesive surface to which a release paper having a cut line to form a cover member is attached, a front cover paperboard to be attached to a front cover region of the adhesive surface, a backbone paperboard to be attached to a backbone region of the adhesive surface, a back cover paperboard to be attached to a back cover region of the adhesive surface, and a body of pages made of a plurality of sheets bound together at one end. The release paper is divided into a front cover release paper, a front cover groove release paper, a backbone release paper, a back cover groove release paper, a back cover release paper, and a flap release paper.

摘要翻译： 为了提供易于使用者制作原始书籍的书本装订工具，它包括由具有打印表面和粘合表面的纸组成的一组，其中附着有具有切割线以形成盖构件的剥离纸， 要粘附到粘合剂表面的前盖区域上的前盖纸板，附着到粘合剂表面的主干区域的主干纸板，附着到粘合剂表面的后盖区域的后盖纸板，以及 在一端结合在一起的多个纸张制成的页面主体。 剥离纸分为前盖释放纸，前盖槽释放纸，主干剥离纸，后盖槽释放纸，后盖释放纸和挡片剥离纸。

公开(公告)号：US5770511A

公开(公告)日：1998-06-23

申请号：US729870

申请日：1996-10-15

申请人： Kei Matsumoto ,  Hirotaka Kato ,  Hiroshi Furukawa

发明人： Kei Matsumoto ,  Hirotaka Kato ,  Hiroshi Furukawa

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L21/2007

摘要： The present invention, a silicon-on-insulator (SOI) substrate and its fabrication method, is suited to the wafer-bonding method. A pre-oxidation treatment accompanying the oxidation treatment and the adhesive thermal treatment to prevent metal impurities from polluting semiconductor wafers. Before an oxide layer is thermally grown on one wafer or after two bonded wafers are subjected to a adhesive thermal treatment at a temperature T1, the pre-oxidation treatment is performed at a temperature of T2, which satisfies the relation equation of T1-300.ltoreq.T2.ltoreq.T1-100 (.degree.C.). Water steam, pure oxygen, or diluted oxygen, is conducted into the furnace, in which the pre-oxidation treatment is performed in an oxidation ambient. Accordingly, an oxide film having a predetermined thickness is formed on the surface of the SOI substrate serving as a barrier for preventing metal impurities, such as Fe, Cr, or the like, from invading the substrate and degrading the electrical characteristics thereof.

摘要翻译： 本发明的绝缘体上硅（SOI）衬底及其制造方法适用于晶片接合方法。 伴随氧化处理和粘合剂热处理的预氧化处理以防止金属杂质污染半导体晶片。 在氧化物层在一个晶片上热生长之前，或者在两个接合的晶片在温度T1进行粘合剂热处理之后，在T2的温度下进行预氧化处理，该温度满足关系式T1-300 < / = T2

公开(公告)号：US08888913B2

公开(公告)日：2014-11-18

申请号：US13206310

申请日：2011-08-09

申请人： Kazuhiro Narahara ,  Hirotaka Kato ,  Koichiro Hayashida

发明人： Kazuhiro Narahara ,  Hirotaka Kato ,  Koichiro Hayashida

IPC分类号： C30B21/02 ,  C30B23/06 ,  C23C16/458 ,  C30B25/12 ,  C23C16/24

CPC分类号： C23C16/24 ,  C23C16/4585 ,  C23C16/4586 ,  C30B23/063 ,  C30B25/12 ,  H01L21/68735

摘要： A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.

摘要翻译： 提供了形成外延层以提高外延硅晶片的平坦度的方法。 特别地，提供了控制晶片周边部分中的外延层厚度的方法。 一种用于通过在反应炉中生长具有半导体晶片和源气体的反应的外延层来制造外延晶片的装置，包括：放置半导体晶片的凹槽; 固定半导体的基座; 取决于半导体晶片的晶体取向和/或独立于半导体晶片的晶体取向的取向非依赖性控制装置的取向依赖控制装置，其中该装置可以改善外延层的外围部分的平坦度。

公开(公告)号：US08021484B2

公开(公告)日：2011-09-20

申请号：US11731815

申请日：2007-03-30

申请人： Kazuhiro Narahara ,  Hirotaka Kato ,  Koichiro Hayashida

发明人： Kazuhiro Narahara ,  Hirotaka Kato ,  Koichiro Hayashida

IPC分类号： C30B21/06

CPC分类号： C23C16/24 ,  C23C16/4585 ,  C23C16/4586 ,  C30B23/063 ,  C30B25/12 ,  H01L21/68735

摘要： A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.

摘要翻译： 提供了形成外延层以提高外延硅晶片的平坦度的方法。 特别地，提供了控制晶片周边部分中的外延层厚度的方法。 一种用于通过在反应炉中生长具有半导体晶片和源气体的反应的外延层来制造外延晶片的装置，包括：放置半导体晶片的凹槽; 固定半导体的基座; 取决于半导体晶片的晶体取向和/或独立于半导体晶片的晶体取向的取向非依赖性控制装置的取向依赖控制装置，其中该装置可以改善外延层的外围部分的平坦度。

公开(公告)号：US06250462B1

公开(公告)日：2001-06-26

申请号：US09434933

申请日：1999-11-05

申请人： Hirotaka Kato

发明人： Hirotaka Kato

IPC分类号： B65D8557

CPC分类号： B42D3/12 ,  B42D1/00 ,  G11B33/0422 ,  G11B33/0494

摘要： Disclosed is a book-like disc casing which comprises a series of a front cover, a spine and a rear cover, made of cardboard, and a plurality of pieces of paper, the front cover, spine and rear cover being folded to be like a book with the pieces of paper interleaved between the front cover and the rear cover. At least one of the front and rear covers has an intermediate member and a lining member laid on each other to form a lamination inside. The intermediate member has a disc accommodating space formed therein, and the lining member has a line of perforations and creases intercepting the line of perforations, which is partly in conformity with the disc accommodating space, thereby facilitating the making of an opening in the lining member to permit the taking-out of the disc from the disc accommodating space.

摘要翻译： 公开了一种书本的盘壳，其包括由纸板制成的一系列前盖，脊柱和后盖，以及多张纸，前盖，脊柱和后盖被折叠成为 与在前盖和后盖之间交错的纸张预订。 前盖和后盖中的至少一个具有彼此叠置以在内部形成层压件的中间构件和衬里构件。 中间构件具有形成在其中的盘容纳空间，并且衬里构件具有一线的穿孔和折痕，其拦截穿孔线，其部分地与盘容纳空间一致，从而有助于在衬里构件中形成开口 以允许从盘容纳空间取出盘。

公开(公告)号：US07993452B2

公开(公告)日：2011-08-09

申请号：US11731268

申请日：2007-03-30

申请人： Koichiro Hayashida ,  Kazuhiro Narahara ,  Hirotaka Kato

发明人： Koichiro Hayashida ,  Kazuhiro Narahara ,  Hirotaka Kato

IPC分类号： C30B21/04

CPC分类号： H01L21/02052 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/68735

摘要： A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer is provided. For example, the method comprises: a pre-cleaning process for cleaning the silicon wafer having top and bottom faces processed to a mirror finish; and a rapid thermal process or an epitaxial growth process, wherein the pre-cleaning process comprises a hydrofluoric acid (HF) process and a subsequent pure water (DIW) process.

摘要翻译： 在硅晶片的制造过程中识别硅晶片的底面的作用。 并且还确定了优选的特征。 为了获得上述特征，提供了一种将在普通硅晶片的制造方法中实施的方法。 例如，该方法包括：用于清洁硅晶片的预清洁工艺，其具有加工成镜面光洁度的顶面和底面; 以及快速热处理或外延生长工艺，其中预清洗工艺包括氢氟酸（HF）工艺和随后的纯水（DIW）工艺。

公开(公告)号：US5897743A

公开(公告)日：1999-04-27

申请号：US786767

申请日：1997-01-21

申请人： Kazuaki Fujimoto ,  Hiroshi Furukawa ,  Hirotaka Kato

发明人： Kazuaki Fujimoto ,  Hiroshi Furukawa ,  Hirotaka Kato

IPC分类号： C30B35/00 ,  B26D3/28 ,  B29C63/00 ,  B32B43/00 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02 ,  H01L21/30 ,  H01L21/304 ,  H01L21/58 ,  H01L27/12 ,  B32B35/00

CPC分类号： B32B43/006 ,  B26D3/282 ,  B29C63/0013 ,  Y10S156/941 ,  Y10T156/11 ,  Y10T156/1179 ,  Y10T156/19 ,  Y10T29/49822 ,  Y10T29/53683

摘要： A peeling jig is provided for peeling a bonded wafer having voids formed in bonding surfaces so as to rebond, which does not injure the bonding surfaces or cause the adherence of particles thereto. The peeling jig includes a wedge portion 1a for inserting into the bonding surfaces, and a flat portion provided at the both sides of the base of the wedge portion. The apex angle of the wedge portion, when the chamfered angles at the bonding sides of the supporting substrate and active wafer of the bonded wafer to be separated are respectively .alpha. and .beta., is .theta. and .theta.>.alpha.+.beta.. When the wedge portion is inserted into the bonding surfaces, the right and left inclined surfaces of the wedge portion are in contact with the peripheries of the chamfered portions, and then chamfered portions are flared. Accordingly, the bonded wafer is separated by the wedge portion into the supporting substrate and the active wafer without being contacted with the bonding surfaces until the flat portions are in contact with the periphery of the bonded wafer.

摘要翻译： 提供一种剥离夹具，用于剥离在接合表面形成的具有空隙的接合晶片，以便重新粘结，这不会损伤接合表面或引起颗粒附着。 剥离夹具包括用于插入接合表面的楔形部分1a和设置在楔形部分的基部两侧的平坦部分。 当待分离的接合晶片的支撑衬底和有源晶片的接合侧的倒角角度分别为α和β时，楔形部分的顶角为θ和θ>α+β。 当楔形部分插入接合表面时，楔形部分的左右倾斜表面与倒角部分的周边接触，然后倒角部分被展开。 因此，接合晶片被楔形部分分离成支撑衬底和活性晶片，而不与接合表面接触，直到平坦部分与接合晶片的周边接触。

公开(公告)号：US06392325B1

公开(公告)日：2002-05-21

申请号：US09284467

申请日：1999-04-20

申请人： Shinichi Fujii ,  Hirotaka Kato ,  Takahiro Harada ,  Haruyuki Ota ,  Seiji Onozaki

发明人： Shinichi Fujii ,  Hirotaka Kato ,  Takahiro Harada ,  Haruyuki Ota ,  Seiji Onozaki

IPC分类号： H02K1304

摘要： A metallic ring 45 molded by punching a copper plate having hooks 43, etc., and a carbon member 46 are brazed to each other by a brazing material having a higher melting point than the temperature for connecting a coil to conductive members 52, that is, a brazing material containing, for example, nickel and chromium. Next, resin is filled up inside the metallic ring 45 and carbon member 46 to form a resin substrate 48. Next, slits 50 are formed at the metallic ring 45 and the carbon member 46 in the radial direction, so that generally fan-shaped segments 51 insulated from each other and conductive members 52 are formed. Next, a coil is connected to hooks 43 of the conductive members 52 by soldering, welding, etc.

公开(公告)号：US5948549A

公开(公告)日：1999-09-07

申请号：US945231

申请日：1997-10-17

申请人： Takemori Takayama ,  Yuichi Hori ,  Hirotaka Kato

发明人： Takemori Takayama ,  Yuichi Hori ,  Hirotaka Kato

IPC分类号： B22F3/10 ,  B22F7/06 ,  B23K35/00 ,  B32B1/00

CPC分类号： B22F7/062 ,  B22F7/06 ,  B23K35/007 ,  B22F2998/00 ,  C22C2204/00 ,  Y10T428/12028 ,  Y10T428/12917

摘要： A sinter-joining method for forming a sinter of high quality at low cost and a sintered composite member produced by the sinter-joining method.A tubular copper-base material is forced into a tubular iron-base material and these materials are sintered at temperatures equal to and higher than 600.degree. C. so that the copper-base material expands and pressure-joins to the iron-base material. Then, the materials are sintered at temperatures equal to and higher than 850.degree. C. so that the compactness of the copper-base material is increased. Through these steps, the sintered composite member containing the copper-base material joined to the inside of the iron-base material is obtained.

摘要翻译： PCT No.PCT / JP96 / 01061 Sec。 371日期1997年10月17日第 102（e）日期1997年10月17日PCT 1996年4月19日PCT PCT。 出版物WO96 / 33036 日期1996年10月24日以低成本形成高品质烧结体的烧结接合方法和通过烧结接合法制造的烧结复合部件。 将管状铜基材料压入管状铁基材料中，并将这些材料在等于或高于600℃的温度下烧结，以使铜基材料膨胀并压接在铁基材料上。 然后，将材料在等于或高于850℃的温度下烧结，使得铜基材料的致密性增加。 通过这些工序，得到含有与铁基材的内侧接合的铜基材料的烧结复合体。

公开(公告)号：US5932048A

公开(公告)日：1999-08-03

申请号：US882348

申请日：1997-06-25

申请人： Hiroshi Furukawa ,  Hirotaka Kato ,  Hiroaki Yamamoto ,  Kazuaki Fujimoto

发明人： Hiroshi Furukawa ,  Hirotaka Kato ,  Hiroaki Yamamoto ,  Kazuaki Fujimoto

IPC分类号： H01L21/18 ,  H01L21/324 ,  H01L21/304

CPC分类号： H01L21/187 ,  Y10S148/003 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159 ,  Y10S438/906 ,  Y10S438/959 ,  Y10S438/964 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S438/977

摘要： A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C. in the period between the bonding step and the annealing step.

摘要翻译： 直接接合半导体晶片的方法限制了接合步骤和接合退火步骤之间的时间间隔，或者在预定温度下在预定时间间隔内在接合和接合退火步骤之间进行烘烤步骤，以防止在 晶圆的边缘区域。 用于制造叠层半导体晶片的方法包括通过粘合夹具将两个抛光的半导体晶片配合在一起的接合步骤，以及随后的结合退火步骤以层压晶片。 在该方法中，接合退火步骤优选在接合步骤后一小时内进行; 或者在接合步骤和接合退火步骤之间进行在预定温度下预定时间间隔的烘烤步骤。 此外，该方法可以在粘合步骤和退火步骤之间的时间段内，通过在100℃以上烘烤晶片超过5分钟来防止附着在晶片表面的重金属杂质扩散到晶片中。