公开(公告)号：US06287912B1

公开(公告)日：2001-09-11

申请号：US09389457

申请日：1999-09-03

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823857 ,  H01L27/10852 ,  H01L27/10873 ,  Y10S438/981

摘要： A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

摘要翻译： 通过图案化光致抗蚀剂膜形成用于蚀刻形成在栅极绝缘膜形成区域中的相对薄的栅极绝缘膜的掩模，并且该掩模用于引入用于调节n沟道场效应晶体管的阈值电压的杂质和p - 沟道场效应晶体管，其具有相对较薄的栅极绝缘膜到半导体衬底上未被掩模覆盖的区域。

公开(公告)号：US06198128B1

公开(公告)日：2001-03-06

申请号：US09390662

申请日：1999-09-07

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

IPC分类号： H01L2972

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823814

摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

摘要翻译： 在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会 被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US20050035428A1

公开(公告)日：2005-02-17

申请号：US10946000

申请日：2004-09-22

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06399453B2

公开(公告)日：2002-06-04

申请号：US09891381

申请日：2001-06-27

申请人： Ryo Nagai ,  Norikatsu Takaura ,  Hisao Asakura

发明人： Ryo Nagai ,  Norikatsu Takaura ,  Hisao Asakura

IPC分类号： H01L21336

CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L27/10873 ,  H01L27/10894

摘要： Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

摘要翻译： 期望的操作特性是从其中使用p型硅栅电极的MISFET获得的，以防止以下列方式将硼泄漏到沟道区中。 通过将磷离子注入到非晶硅中形成N型非晶硅9n。 接着，将硼离子注入n型非晶硅9n中，将其转换为p型非晶硅9p。 然后非晶硅9p结晶。 最后，MISFET的栅电极由在上述步骤中获得的p型多晶硅构成，其中已经注入了磷和硼。

公开(公告)号：US5359221A

公开(公告)日：1994-10-25

申请号：US86096

申请日：1993-07-06

申请人： Masafumi Miyamoto ,  Ryo Nagai ,  Tatsuya Ishii ,  Koichi Seki

发明人： Masafumi Miyamoto ,  Ryo Nagai ,  Tatsuya Ishii ,  Koichi Seki

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66659

摘要： Source and drain regions are formed in first regions of low concentration formed on a surface of a semiconductor surface, and a second region with doping concentration higher than that of the first regions is formed around the first regions. Further in the second region, third regions with doping concentration higher than that of the second region are formed separate from each other. By virtue of this, a rise of the threshold voltage attendant on a decrease of the channel length is canceled out by the third regions and the short channel effect is suppressed. Further, since doping concentration of the first region is low, high carrier mobility can be obtained.

摘要翻译： 源极和漏极区域形成在半导体表面的表面上形成的低浓度的第一区域中，并且在第一区域周围形成掺杂浓度高于第一区域的第二区域。 此外，在第二区域中，掺杂浓度高于第二区域的第三区域形成为彼此分离。 由此，通过第三区域抵消伴随着沟道长度的减小的阈值电压的上升，抑制短路效应。 此外，由于第一区域的掺杂浓度低，因此可以获得高载流子迁移率。

公开(公告)号：US06538945B2

公开(公告)日：2003-03-25

申请号：US10050561

申请日：2002-01-18

申请人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

发明人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10897

摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

公开(公告)号：US20070031094A1

公开(公告)日：2007-02-08

申请号：US11493917

申请日：2006-07-27

申请人： Misao Watahiki ,  Ryo Nagai ,  Takahiro Sato

发明人： Misao Watahiki ,  Ryo Nagai ,  Takahiro Sato

IPC分类号： G02B6/44

CPC分类号： G02B6/4495

摘要： An optical fiber cable has: a cable portion having an optical fiber tape core wire that a plurality of optical fiber core wires are stacked in parallel, and a cable sheath formed on the plurality of optical fiber core wires; and mold-releasing sheets disposed in parallel with the optical fiber tape core wire. The mold-releasing sheets have an end portion extended from the end of the optical fiber tape core wire. An end of the optical fiber tape core wire is covered by the end portion of the mold-releasing sheet.

摘要翻译： 光纤电缆具有：具有多根光纤芯线并列堆叠的光纤带芯线的电缆部分和形成在多根光纤芯线上的电缆护套; 以及与光纤带芯线并联设置的脱模片。 脱模片具有从光纤带芯线的端部延伸的端部。 光纤带芯线的端部被脱模片的端部覆盖。

公开(公告)号：US07057243B2

公开(公告)日：2006-06-06

申请号：US10648883

申请日：2003-08-27

申请人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

发明人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

IPC分类号： H01L29/94

CPC分类号： H01L27/10891 ,  H01L21/28061 ,  H01L21/823842 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4941 ,  H01L29/7833

摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

摘要翻译： 在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。 具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。 具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

公开(公告)号：US20050100773A1

公开(公告)日：2005-05-12

申请号：US10490528

申请日：2003-02-14

申请人： Hiroshi Kashino ,  Yasuo Arishima ,  Shinsuke Shibata ,  Gun Seki ,  Shoji Saibara ,  Ryo Nagai

发明人： Hiroshi Kashino ,  Yasuo Arishima ,  Shinsuke Shibata ,  Gun Seki ,  Shoji Saibara ,  Ryo Nagai

IPC分类号： H01M8/04 ,  H01M8/10 ,  H01M8/24 ,  H01M4/86

CPC分类号： H01M8/1009 ,  H01M8/04186 ,  H01M8/1004 ,  H01M8/2455

摘要： A liquid fuel cell comprising a plurality of unit fuel cells each having a positive electrode (8) for reducing oxygen, a negative electrode (9) for oxidizing liquid fuel, and an electrolyte layer (10) interposed between the positive electrode (8) and the negative electrode (9), and a section (3) for storing liquid fuel (4), wherein power can be generated stably while reducing the size by arranging the plurality of unit fuel cells on the substantially same plane. Each electrolyte layer of the unit fuel cell preferably constitutes a continuous integrated electrolyte layer.

摘要翻译： 一种液体燃料电池，包括多个单元燃料电池，每个单元燃料电池均具有用于还原氧的正电极（8），用于氧化液体燃料的负电极（9）和介于所述正电极（8）和 负极（9）和用于储存液体燃料（4）的部分（3），其中通过将多个单位燃料电池布置在基本相同的平面上，能够稳定地产生功率，同时减小尺寸。 单元燃料电池的每个电解质层优选构成连续的集成电解质层。