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    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance
    9.
    发明授权
    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance 失效
    半导体集成电路器件包括具有增加的信息存储电容的存储单元的存储器件

    公开(公告)号：US5578849A

    公开(公告)日：1996-11-26

    申请号：US341966

    申请日：1994-11-16

    申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

    摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

    摘要翻译： 存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个存储单元具有开关晶体管和信息存储电容器。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。

    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs
    10.
    发明授权
    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
    具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法

    公开(公告)号：US5504029A

    公开(公告)日：1996-04-02

    申请号：US254562

    申请日：1994-06-06

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。 电容器元件的电介质膜与其上的电容器电极层共同扩展。 电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。