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公开(公告)号：US20060226913A1
公开(公告)日：2006-10-12
申请号：US10566240
申请日：2003-07-30
IPC分类号： H03F3/08
CPC分类号： H03G3/3084 , H03F3/08 , H03G1/0047 , H03G2201/103 , H03G2201/502 , H04B10/69
摘要： A gain switching circuit switches a conversion gain of a preamplifier that is configured with a series circuit formed with a first resistor and a first switching element and a series circuit formed with a second resistor and a second switching element respectively connected in parallel with a feedback resistor. The gain switching circuit includes a first operating unit that generates a first switching element operating signal for closing the first switching element within a first gain switching period, and a second operating unit that generates a second switching element operating signal for closing the second switching element within a second gain switching period.
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公开(公告)号：US06215368B1
公开(公告)日：2001-04-10
申请号：US09337730
申请日：1999-06-22
申请人： Hitoyuki Tagami , Kuniaki Motoshima
发明人： Hitoyuki Tagami , Kuniaki Motoshima
IPC分类号： H03B512
CPC分类号： H03K3/0322 , H03K3/0231 , H03K3/03
摘要： Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolator and into the delay unit. The delay unit delays the signal by d1 and inputs into second input terminal of the delay interpolator. Oscillation frequency control voltage is fed into a terminal of the delay interpolator through an oscillation frequency control terminal of the device. Delay control voltage is fed into a terminal of the device in order to control a propagation delay rate in the delay unit and the delay interpolator. The delay rate in a delay unit and a delay interpolator can be adjusted by a delay control voltage.
摘要翻译： 电压控制/振荡装置包括用于设置延迟单元和延迟内插器中的延迟速率的端子。 相位被反相门反相的时钟信号被输入到延迟内插器的第一输入端并进入延迟单元。 延迟单元将信号延迟d1并输入到延迟插值器的第二输入端。 振荡频率控制电压通过器件的振荡频率控制端子馈送到延迟插补器的端子。 延迟控制电压被馈送到设备的终端中，以便控制延迟单元和延迟内插器中的传播延迟速率。 可以通过延迟控制电压来调整延迟单元和延迟内插器中的延迟率。
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公开(公告)号：US07598479B2
公开(公告)日：2009-10-06
申请号：US10566240
申请日：2003-07-30
IPC分类号： H03F3/08
CPC分类号： H03G3/3084 , H03F3/08 , H03G1/0047 , H03G2201/103 , H03G2201/502 , H04B10/69
摘要： A gain switching circuit switches a conversion gain of a preamplifier that is configured with a series circuit formed with a first resistor and a first switching element and a series circuit formed with a second resistor and a second switching element respectively connected in parallel with a feedback resistor. The gain switching circuit includes a first operating unit that generates a first switching element operating signal for closing the first switching element within a first gain switching period, and a second operating unit that generates a second switching element operating signal for closing the second switching element within a second gain switching period.
摘要翻译： 增益切换电路切换配置有由第一电阻器和第一开关元件形成的串联电路的前置放大器的转换增益，以及与分别与反馈电阻并联连接的第二电阻器和第二开关元件形成的串联电路 。 增益切换电路包括第一操作单元，其在第一增益切换周期内产生用于闭合第一开关元件的第一开关元件操作信号，以及第二操作单元，其产生用于闭合第二开关元件的第二开关元件操作信号 第二增益切换周期。
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公开(公告)号：US06249160B1
公开(公告)日：2001-06-19
申请号：US09376496
申请日：1999-08-18
申请人： Hitoyuki Tagami , Kuniaki Motoshima
发明人： Hitoyuki Tagami , Kuniaki Motoshima
IPC分类号： H03K501
CPC分类号： H03L7/07 , H03L7/06 , H03L7/0807 , H04L7/027 , H04L7/0337
摘要： In a clock reproduction and identification device, a clock extraction circuit extracts a transmission line clock from input data and a phase synchronization section reproduces an identification clock synchronized with the transmission line clock in frequency and phase. An identification section identifies the input data based on the identification clock.
摘要翻译： 在时钟再现和识别装置中，时钟提取电路从输入数据中提取传输线时钟，相位同步部分在频率和相位上再现与传输线时钟同步的识别时钟。 识别部分基于识别时钟识别输入数据。
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公开(公告)号：US20100164575A1
公开(公告)日：2010-07-01
申请号：US12377081
申请日：2006-09-04
CPC分类号： H04L7/0338 , H04L7/04
摘要： Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigger, data discriminating and reproducing circuits for outputting sampled data of the input data which are synchronized with the clocks, a continuous clock generation circuit for generating a continuous clock which is a reference clock, continuous clock synchronization circuits for synchronizing the sampled data with the continuous clock and outputting the synchronized sampled data as phase synchronization data, and a phase selector for selecting the phase synchronization data having an optimum discrimination phase with the largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.
摘要翻译： 提供了一种数据恢复电路，包括输入数据相位检测电路，用于输出与输入数据的上升相位同步的门信号，门控多相振荡器，用于基于门信号作为触发立即产生N相时钟，数据识别和 用于输出与时钟同步的输入数据的采样数据的再现电路，用于产生作为参考时钟的连续时钟的连续时钟产生电路，用于使采样数据与连续时钟同步的连续时钟同步电路，并输出同步 采样数据作为相位同步数据，以及相位选择器，用于相对于输入数据选择具有最大相位裕度的最佳鉴别相位的相位同步数据，并输出所选择的相位同步数据作为恢复数据。
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公开(公告)号：US07489757B2
公开(公告)日：2009-02-10
申请号：US10517493
申请日：2003-05-01
申请人： Hirofumi Totsuka , Hitoyuki Tagami
发明人： Hirofumi Totsuka , Hitoyuki Tagami
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/08 , H03L7/081 , H03L7/091 , H04L7/0037 , H04L7/0041 , H04L7/033 , H04L7/0337
摘要： A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.
摘要翻译： 分频器通过划分输入数据的频率来产生分频输入数据。 相位比较器检测由压控振荡器产生的时钟的相位与分频输入数据的相位之间的相位差，并产生用于消除所检测的相位差的相位差信号。 电压控制振荡器通过基于相位差信号调整振荡频率来产生时钟。 数据标识符使用由压控振荡器产生的时钟识别输入数据。
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公开(公告)号：US20050213696A1
公开(公告)日：2005-09-29
申请号：US10517493
申请日：2003-05-01
申请人： Hirofumi Totsuka , Hitoyuki Tagami
发明人： Hirofumi Totsuka , Hitoyuki Tagami
CPC分类号： H03L7/07 , H03L7/08 , H03L7/081 , H03L7/091 , H04L7/0037 , H04L7/0041 , H04L7/033 , H04L7/0337
摘要： A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.
摘要翻译： 分频器通过划分输入数据的频率来产生分频输入数据。 相位比较器检测由压控振荡器产生的时钟的相位与分频输入数据的相位之间的相位差，并产生用于消除所检测的相位差的相位差信号。 电压控制振荡器通过基于相位差信号调整振荡频率来产生时钟。 数据标识符使用由压控振荡器产生的时钟识别输入数据。
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公开(公告)号：US20070229118A1
公开(公告)日：2007-10-04
申请号：US11504694
申请日：2006-08-16
IPC分类号： H03D13/00
CPC分类号： H03D13/003
摘要： A phase comparator includes: first and second detecting units for detecting an amplitude value of a clock signal at falling timing or rising timing of a data signal; an edge comparing unit for identifying as to whether the first detecting unit detects an amplitude value under a rising state or a falling state to output a first identification result, and for identifying as to whether the second detecting unit detects an amplitude value under a rising state or a falling state to output a second identification result; first and second polarity inverting units for inverting a polarity of output of the first and second detecting units; and a signal selecting unit for selecting one of output values of the first and second polarity inverting units in response to a polarity of the data signal to output the selected output value.
摘要翻译： 相位比较器包括：第一和第二检测单元，用于检测下降定时时钟信号的振幅值或数据信号的上升定时; 边缘比较单元，用于识别第一检测单元是否在升高状态或下降状态下检测振幅值以输出第一识别结果，并且用于识别第二检测单元是否在升高状态下检测振幅值 或下降状态输出第二识别结果; 第一和第二极性反转单元，用于反转第一和第二检测单元的输出的极性; 以及信号选择单元，用于响应于数据信号的极性来选择第一和第二极性反转单元的输出值之一，以输出所选择的输出值。
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公开(公告)号：US06580300B2
公开(公告)日：2003-06-17
申请号：US10098521
申请日：2002-03-18
申请人： Hitoyuki Tagami
发明人： Hitoyuki Tagami
IPC分类号： H03H1116
CPC分类号： H03B27/00
摘要： The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.
摘要翻译： 多相信号发生器包括对输入信号增加第一预定相位延迟的第一延迟电路，产生具有根据输入到一个端子的输入信号之间的相位差规定的输出相位的第一输出信号的第一相位内插电路 以及输入到从所述延迟加法单元输出的所述第一输出信号生成单元的另一端子的信号;以及第二相位插值电路，其生成具有根据所述延迟加法单元规定的输出相位的第二输出信号 输入到从延迟加法单元输出的第二输出信号生成单元的一个端子的信号与输入到第二输出信号生成单元的另一端子的输入信号的反相信号之间的相位差。
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公开(公告)号：US06566852B2
公开(公告)日：2003-05-20
申请号：US09921870
申请日：2001-08-06
申请人： Hitoyuki Tagami , Koichi Takizawa
发明人： Hitoyuki Tagami , Koichi Takizawa
IPC分类号： G05F316
摘要： The voltage generator includes the NPN transistor that flows a current corresponding to a voltage VOP output from the error detector. Furthermore, there is provided the current mirror circuit which includes two PNP transistors that flow currents which are multiples of the current that the NPN transistor flows. Furthermore, there are provided two resistors for generating a feedback voltage VFBK to the error detector from an output voltage VREG generated based on a current that the current mirror circuit flows.
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