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    SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS
    2.
    发明申请
    SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS 有权
    具有活动区域和方法之间的隔离区域的电压插入源/漏区

    公开(公告)号：US20130168756A1

    公开(公告)日：2013-07-04

    申请号：US13343087

    申请日：2012-01-04

    申请人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

    发明人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

    摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

    摘要翻译： 公开了设备，存储器阵列和方法。 在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。 电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

    Source/drain zones with a delectric plug over an isolation region between active regions and methods
    3.
    发明授权
    Source/drain zones with a delectric plug over an isolation region between active regions and methods 有权
    源极/漏极区域在有源区域之间的隔离区域和方法之间具有绝缘插头

    公开(公告)号：US08907396B2

    公开(公告)日：2014-12-09

    申请号：US13343087

    申请日：2012-01-04

    申请人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

    发明人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

    摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

    摘要翻译： 公开了设备，存储器阵列和方法。 在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。 电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

    FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED
    5.
    发明申请
    FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED 有权
    在存储器阵列和存储器阵列中形成空气流量，形成空气GAPS

    公开(公告)号：US20130026600A1

    公开(公告)日：2013-01-31

    申请号：US13192763

    申请日：2011-07-28

    申请人： James Matthew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

    发明人： James Matthew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

    IPC分类号： H01L29/06 ,  H01L21/764

    CPC分类号： H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

    摘要： Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

    摘要翻译： 公开了在如此形成的具有气隙的存储器阵列和存储器阵列中形成气隙的方法。 一种这样的方法可以包括通过半导体上的电荷存储结构形成具有第一电介质的隔离区域，所述隔离区域延伸到半导体中; 在隔离区域和电荷存储结构上形成第二电介质; 并且在隔离区域中形成气隙，使得气隙通过电荷存储结构，并且第一电介质的厚度在气隙和第二电介质之间。

    Forming air gaps in memory arrays and memory arrays with air gaps thus formed
    7.
    发明授权
    Forming air gaps in memory arrays and memory arrays with air gaps thus formed 有权
    在由此形成的气隙的存储器阵列和存储器阵列中形成气隙

    公开(公告)号：US08569130B2

    公开(公告)日：2013-10-29

    申请号：US13192763

    申请日：2011-07-28

    申请人： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

    发明人： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

    摘要： Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

    摘要翻译： 公开了在如此形成的具有气隙的存储器阵列和存储器阵列中形成气隙的方法。 一种这样的方法可以包括通过半导体上的电荷存储结构形成具有第一电介质的隔离区域，所述隔离区域延伸到半导体中; 在隔离区域和电荷存储结构上形成第二电介质; 并且在隔离区域中形成气隙，使得气隙通过电荷存储结构，并且第一电介质的厚度在气隙和第二电介质之间。

    Methods of fabricating a memory device
    8.
    发明授权
    Methods of fabricating a memory device 有权
    制造存储器件的方法

    公开(公告)号：US08222105B2

    公开(公告)日：2012-07-17

    申请号：US12703502

    申请日：2010-02-10

    申请人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

    发明人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

    摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

    摘要翻译： 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。 在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

    Fin structures and methods of fabricating fin structures
    9.
    发明授权
    Fin structures and methods of fabricating fin structures 有权
    鳍结构和制造鳍结构的方法

    公开(公告)号：US08076721B2

    公开(公告)日：2011-12-13

    申请号：US12795495

    申请日：2010-06-07

    申请人： Sahn D. Tang ,  Gordon Haller

    发明人： Sahn D. Tang ,  Gordon Haller

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

    摘要： There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

    摘要翻译： 提供了用于制造翅片结构的翅片结构和方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

    One-transistor memory cell with bias gate
    10.
    发明授权
    One-transistor memory cell with bias gate 有权
    具有偏置栅极的单晶体管存储单元

    公开(公告)号：US07589995B2

    公开(公告)日：2009-09-15

    申请号：US11516814

    申请日：2006-09-07

    申请人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。