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公开(公告)号：US5663924A
公开(公告)日：1997-09-02
申请号：US572604
申请日：1995-12-14
CPC分类号： G11C7/1072 , G11C7/1018
摘要： A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.
摘要翻译： 具有n位突发传输块长度的同步动态随机存取存储器（SDRAM）的边界独立解码器。 用户，通常是处理器或微处理器请求访问一块SDRAM存储器。 所请求的块可以在阵列解码边界之间开始。 列地址由SDRAM列解码器解码。 解码器为2n位选择起始边界。 第一个请求位在2n个选定位的前n位。 因此，整个n位块被包括在所选择的2n位块中。 从选定的2n位中选择n位块，并以顺序加扰的顺序锁存在高速解码器/寄存器中，即第i个位是第一个请求位，并且所请求的位顺序为i。 。 。 ，（n-1），。 。 。 ，0，。 。 。 ，（i-1）。 如果需要，锁存数据按顺序或交错进行加扰。 加扰数据是芯片外的突发传输。
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公开(公告)号：US5961653A
公开(公告)日：1999-10-05
申请号：US803053
申请日：1997-02-19
申请人： Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
发明人： Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
CPC分类号： G06F11/2635 , G11C29/12 , G11C29/32
摘要： An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.
摘要翻译： 具有嵌入在逻辑中的DRAM的集成芯片通过原位处理器定向的BIST宏进行测试。 BIST提供两个ROMS，一个用于存储测试指令，另一个用于存储测试指令，第二个可扫描，为存储在第一个ROM中的测试指令提供顺序，以及分支和循环功能。 此外，BIST宏还具有用于监视DRAM内的故障并用于替换失败的字和/或数据线的冗余分配逻辑部分。 通过将DRAM以0.5mb的增量叠加到4.0mb的最大值或以1.0mb的增量最大为8mb的最大值，所有这些都由BIST宏控制和测试，具有高度粒度的定制芯片设计可以是 实现并针对更大的ASIC中的特定应用量身定做。
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3.发明授权Integrated circuit chip with a wide I/O memory array and redundant data lines 失效具有宽I / O存储器阵列和冗余数据线的集成电路芯片
公开(公告)号：US5796662A
公开(公告)日：1998-08-18
申请号：US756614
申请日：1996-11-26
CPC分类号： G11C29/848
摘要： An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at least one more element than the number of bits in the wide data path; selection logic for deselecting defective data elements; and, switches for selectively coupling each bit of the wide I/O data path to one element or to an element adjacent the one element responsive to the selection means. The integrated circuit chip may further include drive means for selectively driving data from the switches to the element or, otherwise, passing data from the elements to the switches. The switches preferably are three-way switches, such as three CMOS pass gates.
摘要翻译： 具有RAM的集成电路芯片，RAM宏或位片数据逻辑以及至少一个备用阵列元件或备用片元件及其冗余方案。 芯片包括具有诸如位片元件或存储器元件的多个可互换元件的宽数据路径以及与宽数据路径中的位数比至少一个元素; 用于取消选择有缺陷的数据元素的选择逻辑; 以及用于响应于选择装置选择性地将宽I / O数据路径的每一位耦合到一个元件或与该元件相邻的元件的开关。 集成电路芯片还可以包括用于选择性地将数据从开关驱动到元件的驱动装置，或者否则将数据从元件传递到开关。 开关优选地是三路开关，例如三个CMOS通孔。
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公开(公告)号：US07382672B2
公开(公告)日：2008-06-03
申请号：US11754422
申请日：2007-05-29
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。
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公开(公告)号：US06791348B2
公开(公告)日：2004-09-14
申请号：US10208339
申请日：2002-07-29
IPC分类号： G01R3102
CPC分类号： G01R31/2884
摘要： An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.
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6.发明授权公开(公告)号：US07989865B2
公开(公告)日：2011-08-02
申请号：US12200538
申请日：2008-08-28
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。
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公开(公告)号：US07954028B2
公开(公告)日：2011-05-31
申请号：US12046508
申请日：2008-03-12
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.
摘要翻译： 一种用于在集成电路芯片的存储器宏中实现冗余编程的设计结构。 假设所有故障都是行故障，直到确定为位线故障，用于实现其中假定全部故障的方法的电路是行失败，直到确定为位线失败，并且当a = 1时将测试模式传回故障检测电路 测试图案的字线目的地已经被确定为失败，并且测试图案和结果图案通过将存储器宏连接到所述集成电路芯片中的其它电路的逻辑路径在存储器宏和测试引擎之间传递。
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8.发明授权Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction 失效通过光学邻近校正对光刻和反应离子蚀刻图像的保真度增强
公开(公告)号：US5740068A
公开(公告)日：1998-04-14
申请号：US655790
申请日：1996-05-30
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , H01L21/027 , G03F7/00 , H01J37/304
CPC分类号： G03F7/70441 , G03F1/36
摘要： A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.
摘要翻译： 公开了一种用于执行光学邻近校正的方法，其不仅将光学邻近校正限制到电气相关结构，而且还通过处理单个特征边缘来提高校正的精度，并且通过避免将点动灯引入到接近校正中来最小化掩模制造影响 设计。 对相关电气结构的临界边缘区域进行分析，分类和操作以接收光学邻近校正。
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公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
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公开(公告)号：US07920434B2
公开(公告)日：2011-04-05
申请号：US12199438
申请日：2008-08-27
IPC分类号： G11C5/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.
摘要翻译： 提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。 在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。 感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。
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