公开(公告)号：US20110036620A1

公开(公告)日：2011-02-17

申请号：US12563975

申请日：2009-09-21

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/11 ,  B23K1/20

CPC classification number: H05K3/3457 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/4092 ,  H05K3/4644 ,  H05K2201/0397 ,  H05K2201/092 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2203/043

Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.

Abstract translation: 本发明提供一种印刷电路板及其制造方法。 印刷电路板包括具有内部电路结构的基板。 附加的电路结构设置在基板上，电连接到内部电路结构。 具有开口的焊接掩模绝缘层设置在附加电路结构上。 导电凸块图案设置在焊料掩模绝缘层中，其中导电凸块图案水平地延伸到开口中，其中导电凸块图案的一侧，上表面的一部分和下表面的一部分从 从开幕开幕。 在开口中形成焊球，其中焊球与附加电路结构电连接。

公开(公告)号：US08378225B2

公开(公告)日：2013-02-19

申请号：US12563975

申请日：2009-09-21

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/03

CPC classification number: H05K3/3457 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/4092 ,  H05K3/4644 ,  H05K2201/0397 ,  H05K2201/092 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2203/043

Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.

Abstract translation: 本发明提供一种印刷电路板及其制造方法。 印刷电路板包括具有内部电路结构的基板。 附加的电路结构设置在基板上，电连接到内部电路结构。 具有开口的焊接掩模绝缘层设置在附加电路结构上。 导电凸块图案设置在焊料掩模绝缘层中，其中导电凸块图案水平地延伸到开口中，其中导电凸块图案的一侧，上表面的一部分和下表面的一部分从 开放 在开口中形成焊球，其中焊球与附加电路结构电连接。

公开(公告)号：US07528482B2

公开(公告)日：2009-05-05

申请号：US11672507

申请日：2007-02-07

Applicant: Cheng-Hung Huang ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

Inventor： Cheng-Hung Huang ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

IPC: H01L23/10

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Abstract translation: 芯片衬底封装（CiSP）包括双面金属敷层层压板，其包括介电插入件，层叠在电介质插入件的第一侧上的第一金属箔和层叠在电介质插入件的第二侧上的第二金属箔 。 凹入的腔被蚀刻到第二金属箔和电介质插入件中，第一金属箔的一部分作为其底部。 模具安装在凹腔内并与第一金属箔热接触。 堆积材料层覆盖第二金属箔和模具的有效表面。 堆积材料层还填充了管芯和电介质插入件之间的间隙。 至少一个互连层设置在积层材料层上，并且通过电镀通孔与设置在管芯的有效表面上的焊盘电连接。

公开(公告)号：US20080149732A1

公开(公告)日：2008-06-26

申请号：US11673596

申请日：2007-02-12

Applicant: Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

Inventor： Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

IPC: G06K19/067

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K2201/09481 ,  H05K2201/09927

Abstract: A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.

Abstract translation: 许多可追溯的印刷电路板（PCB）包括其上具有图案化电路层的基板和承载与PCB本身相关的生产信息的工作区。 工作区域包括多个代码框，其中每个代码框具有第一探测区域和第二探测区域。 单个电阻测试环路设置在第一探测区域内。 四组电阻测试环设置在第二探针区域内。 使用油炸探针测试仪分别探测一组电阻测试回路，以抽取记录在工作区域中的生产信息。

公开(公告)号：US08420954B2

公开(公告)日：2013-04-16

申请号：US12956724

申请日：2010-11-30

Applicant: Hsien-Chieh Lin ,  Tung-Yu Chang

Inventor： Hsien-Chieh Lin ,  Tung-Yu Chang

IPC: H05K1/11

CPC classification number: H05K1/0203 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/15153 ,  H05K1/0272 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/1469 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.

Abstract translation: 本发明提供一种印刷电路板及其制造方法。 印刷电路板包括具有第一表面和相对的第二表面的芯基板。 分别从第一表面和第二表面穿过芯基板的一部分形成第一通孔和第二通孔，其中第一和第二通孔垂直地层叠并且彼此连接。 第一导轨和第二导轨分别通过芯基板的一部分形成并连接到第二通孔，使得流体从印刷电路板的外部依次流过第一导轨， 第二通孔和第二导轨，连接到印刷电路板的外部。

公开(公告)号：US20110220403A1

公开(公告)日：2011-09-15

申请号：US12762093

申请日：2010-04-16

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/11

CPC classification number: H05K3/403 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/10446 ,  H01L2924/00

Abstract: The invention provides a side packaged type printed circuit board. The side packaged type printed circuit board includes a circuit substrate having a surface and an adjacent side surface. An inner circuit covers a portion of the surface. A first side electrical connecting pad electrically connects to the inner circuit, wherein the first side electrical connecting pad and the inner circuit are in the same additional layer.

Abstract translation: 本发明提供一种侧面封装型印刷电路板。 侧面封装型印刷电路板包括具有表面和相邻侧表面的电路基板。 内部电路覆盖表面的一部分。 第一侧电连接垫电连接到内部电路，其中第一侧电连接焊盘和内部电路处于相同的附加层中。

公开(公告)号：US20110100695A1

公开(公告)日：2011-05-05

申请号：US12646904

申请日：2009-12-23

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/099 ,  Y02P70/611 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.

Abstract translation: 公开了一种印刷电路板结构，其通过提供芯板来制造，在芯板表面上形成内部电路层，在内部电路上形成接合焊盘，在接合焊盘上形成环状抗蚀刻层， 在所述环形防蚀层和所述接合焊盘上形成防焊绝缘层，并且形成用于暴露所述接合焊盘的一部分的开口，其中所述开口的半径比所述环形防蚀层的半径小 抗蚀刻层，并且焊盘表面没有凹陷。 所描述的结构可以防止焊料沿着防焊绝缘层的底部空隙延伸到其它区域。

公开(公告)号：US20080116569A1

公开(公告)日：2008-05-22

申请号：US11672507

申请日：2007-02-07

Applicant: Cheng-Hung Huang ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

Inventor： Cheng-Hung Huang ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

IPC: H01L23/34

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Abstract translation: 芯片衬底封装（CiSP）包括双面金属敷层层压板，其包括介电插入件，层叠在电介质插入件的第一侧上的第一金属箔和层叠在电介质插入件的第二侧上的第二金属箔 。 凹入的腔被蚀刻到第二金属箔和电介质插入件中，第一金属箔的一部分作为其底部。 模具安装在凹腔内并与第一金属箔热接触。 堆积材料层覆盖第二金属箔和模具的有效表面。 堆积材料层还填充了管芯和电介质插入件之间的间隙。 至少一个互连层设置在积层材料层上，并且通过电镀通孔与设置在管芯的有效表面上的焊盘电连接。

公开(公告)号：US07576287B2

公开(公告)日：2009-08-18

申请号：US11673596

申请日：2007-02-12

Applicant: Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

Inventor： Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

IPC: H05K1/00

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K2201/09481 ,  H05K2201/09927

Abstract: A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.

Abstract translation: 许多可追溯的印刷电路板（PCB）包括其上具有图案化电路层的基板和承载与PCB本身相关的生产信息的工作区。 工作区域包括多个代码框，其中每个代码框具有第一探测区域和第二探测区域。 单个电阻测试环路设置在第一探测区域内。 四组电阻测试环设置在第二探针区域内。 使用油炸探针测试仪分别探测一组电阻测试回路，以抽取记录在工作区域中的生产信息。

公开(公告)号：US20080251917A1

公开(公告)日：2008-10-16

申请号：US11752934

申请日：2007-05-24

Applicant: Chih-Chung Chu ,  Shih-Tsung Lin ,  Hsien-Chieh Lin

Inventor： Chih-Chung Chu ,  Shih-Tsung Lin ,  Hsien-Chieh Lin

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/099 ,  H05K2203/0574 ,  H01L2924/00

Abstract: A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer.

Abstract translation: 焊盘结构包括设置在绝缘层上的第一金属层，其中第一金属层通过布置在绝缘层中的导电通孔与下层互连电路层电连接。 具有暴露第一金属层的中心部分的开口的阻焊层设置在绝缘层上。 柱形的第二金属层直接设置在第一金属层的开口内。 填充到开口中的焊球与柱状的第二金属层接触。