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22 条记录 (耗时 0.025 秒)

    Methods of forming semiconductor structures
    1.
    发明授权
    Methods of forming semiconductor structures 有权
    形成半导体结构的方法

    公开(公告)号：US08466070B2

    公开(公告)日：2013-06-18

    申请号：US13151806

    申请日：2011-06-02

    申请人： Hsing-Fei Chou ,  Chia-Hua Chu ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Hung Chang Hsieh

    发明人： Hsing-Fei Chou ,  Chia-Hua Chu ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Hung Chang Hsieh

    IPC分类号： H01L21/311

    CPC分类号： B81C1/00063

    摘要： A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

    摘要翻译： 形成半导体结构的方法包括在衬底中形成开口。 形成介电层并基本上与开口保持一致。 在开口内形成牺牲结构，覆盖电介质层的一部分。 通过使用牺牲结构作为蚀刻掩模层来去除介电层的一部分。 牺牲结构被去除。

    Planarization method for high wafer topography
    2.
    发明授权
    Planarization method for high wafer topography 有权
    高晶圆地形平面化方法

    公开(公告)号：US08409456B2

    公开(公告)日：2013-04-02

    申请号：US13090763

    申请日：2011-04-20

    申请人： Shun-Wei Lan ,  Jieh-Jang Chen ,  Shih-Wei Lin ,  Feng-Jia Shiu ,  Hung Chang Hsieh

    发明人： Shun-Wei Lan ,  Jieh-Jang Chen ,  Shih-Wei Lin ,  Feng-Jia Shiu ,  Hung Chang Hsieh

    IPC分类号： B44C1/22

    CPC分类号： H01L21/31058 ,  H01L21/31138

    摘要： A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

    摘要翻译： 一种用于平面化半导体器件的方法包括提供其中具有至少一个开口的衬底，每个开口限定下部和上部; 在所述基板上涂覆感光材料层，所述光敏材料层覆盖所述至少一个开口的下部和上部; 蚀刻光敏材料层以暴露至少一个开口的上部; 重复涂覆和蚀刻步骤以除去至少一个开口的上部下方的预定量; 在衬底上沉积绝缘层; 并且平坦化绝缘层，直到暴露至少一个开口的上部。

    Manufacturing techniques to limit damage on workpiece with varying topographies
    3.
    发明授权
    Manufacturing techniques to limit damage on workpiece with varying topographies 有权
    制造技术来限制对具有不同形貌的工件的损伤

    公开(公告)号：US08623229B2

    公开(公告)日：2014-01-07

    申请号：US13306299

    申请日：2011-11-29

    申请人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung Chang Hsieh

    发明人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung Chang Hsieh

    IPC分类号： B44C1/22

    CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L27/11541 ,  H01L29/66795

    摘要： Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

    摘要翻译： 一些实施例涉及用于处理工件的方法。 在该方法中，在工件上设置第一光致抗蚀剂层，其中第一光致抗蚀剂层具有第一光致抗蚀剂色调。 图案化第一光致抗蚀剂层以提供暴露工件的第一部分的第一开口。 然后在图案化的第一光致抗蚀剂层上提供第二光致抗蚀剂层，其中第二光致抗蚀剂层具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调。 然后对第二光致抗蚀剂层进行图案化以提供与第一开口至少部分重叠的第二开口，以限定重合的工件区域。 然后对同时暴露的工件区域进行处理。 还公开了其他实施例。

    MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES
    6.
    发明申请
    MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES 有权
    制造技术限制工件损坏与变化的地形

    公开(公告)号：US20130137266A1

    公开(公告)日：2013-05-30

    申请号：US13306299

    申请日：2011-11-29

    申请人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung Chang Hsieh

    发明人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung Chang Hsieh

    IPC分类号： H01L21/311

    CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L27/11541 ,  H01L29/66795

    摘要： Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

    摘要翻译： 一些实施例涉及用于处理工件的方法。 在该方法中，在工件上设置第一光致抗蚀剂层，其中第一光致抗蚀剂层具有第一光致抗蚀剂色调。 图案化第一光致抗蚀剂层以提供暴露工件的第一部分的第一开口。 然后在图案化的第一光刻胶层上提供第二光致抗蚀剂层，其中第二光致抗蚀剂层具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调。 然后对第二光致抗蚀剂层进行图案化以提供与第一开口至少部分重叠的第二开口，以限定重合的工件区域。 然后对同时暴露的工件区域进行处理。 还公开了其他实施例。

    System and method for manufacturing a mask for semiconductor processing
    8.
    发明授权
    System and method for manufacturing a mask for semiconductor processing 有权
    用于制造半导体处理用掩模的系统和方法

    公开(公告)号：US07999910B2

    公开(公告)日：2011-08-16

    申请号：US11115433

    申请日：2005-04-27

    申请人： Chia-Jen Chen ,  Hsin-Chang Lee ,  Sheng-Chi Chin ,  Hung Chang Hsieh ,  Burn Jeng Lin

    发明人： Chia-Jen Chen ,  Hsin-Chang Lee ,  Sheng-Chi Chin ,  Hung Chang Hsieh ,  Burn Jeng Lin

    IPC分类号： G03B27/32 ,  G03B27/58 ,  G03D5/00

    CPC分类号： G03F7/38

    摘要： The present disclosure provides a system and method for manufacturing a mask for semiconductor processing. In one example, the system includes at least one exposure unit configured to select a recipe for a later baking process in a post treatment unit, a buffer unit coupled to the exposure unit and configured to move the mask substrate from the exposure unit to the post treatment unit without exposing the mask substrate to the environment; and the post treatment unit coupled to the buffer unit and the exposure unit and configured to perform a baking process on the mask substrate using baking parameters associated with the recipe selected by the exposure unit.

    摘要翻译： 本公开提供了一种用于制造用于半导体处理的掩模的系统和方法。 在一个示例中，系统包括至少一个曝光单元，其被配置为在后处理单元中选择用于稍后烘焙处理的配方，缓冲单元，其耦合到曝光单元并且被配置为将掩模基板从曝光单元移动到柱 处理单元，而不将掩模基板暴露于环境中; 以及所述后处理单元，其耦合到所述缓冲单元和所述曝光单元，并且被配置为使用与由所述曝光单元选择的所述配方相关联的烘焙参数对所述掩模基板进行烘烤处理。