公开(公告)号：US20160035689A1

公开(公告)日：2016-02-04

申请号：US14810043

申请日：2015-07-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huili FU ,  Song GAO

IPC: H01L23/00 ,  H01L23/31 ,  H05K13/04 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01G2/065 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16227 ,  H01L2224/16268 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

Abstract translation: 本发明提供一种芯片集成模块，其包括芯片，无源器件和连接片，其中芯片设置有芯片接合部分，无源器件设置有无源器件接合部分，芯片接合部分 无源器件的管芯和被动器件接合部分彼此相对设置，并且连接件设置在管芯接合部分和无源器件接合部分之间，并连接到管芯接合部分和无源器件接合部分 。 本发明的芯片集成模块实现了易于集成并且成本低廉。 此外，将裸片与无源器件连接的路径变短，可以提高无源器件的性能。 本发明还公开了一种芯片封装结构和芯片集成方法。

公开(公告)号：US20150357307A1

公开(公告)日：2015-12-10

申请号：US14729316

申请日：2015-06-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huili FU ,  Xiaodong ZHANG

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014

Abstract: A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a package layer and a first routing layer, where the package layer includes at least two dies and an attaching part configured to attach the at least two dies, where the attaching part is provided with multiple vias, with a part of vias in the multiple vias disposed at an outer periphery of the at least two dies, and the other part of vias in the multiple vias disposed between the at least two dies, and the first routing layer electrically connects the at least two dies; where the package layer is located between the first routing layer and the first chip, an electrically conductive material is provided in the multiple vias.

Abstract translation: 芯片堆叠封装结构包括第一芯片和第二芯片，其中第二芯片与第一芯片堆叠，并且第二芯片包括封装层和第一布线层，其中封装层包括至少两个模具和附接 部件，其构造成附接所述至少两个模具，其中所述附接部件设置有多个通孔，所述多个通孔中的多个通孔中的一部分通孔设置在所述至少两个模具的外周边，并且所述多个通孔中的另一部分通孔 设置在所述至少两个管芯之间的通孔，并且所述第一布线层电连接所述至少两个管芯; 其中封装层位于第一布线层和第一芯片之间，在多个通孔中提供导电材料。