公开(公告)号：US07776714B2

公开(公告)日：2010-08-17

申请号：US10558621

申请日：2004-06-03

Applicant: Hubert Moriceau ,  Chrystelle Lagahe ,  Benoit Bataillou

Inventor： Hubert Moriceau ,  Chrystelle Lagahe ,  Benoit Bataillou

IPC: H01L21/30

CPC classification number: H01L21/76254

Abstract: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate at an interface, implantation of gaseous species in the thick layer of first material to create a weakened zone delimiting said thin layer between the interface and the weakened zone, deposit a layer of third material called the self-supporting layer on the thick layer made of first material, fracture within the structure composed of the final substrate, the thick layer of first material and the layer of third material, at the weakened zone to supply the substrate supporting said thin layer.

Abstract translation: 本发明涉及一种获得由第二材料制成的基板上由第一材料制成的薄层的方法，所述第二材料被称为最终基板，包括以下步骤：将第一材料的厚层在其主面之一 在界面处的最终底物，在第一材料的厚层中注入气态物质以产生限定界面和弱化区之间的所述薄层的弱化区，在厚层上沉积称为自支撑层的第三材料层 由第一材料制成，在由最终基底构成的结构内的断裂，第一材料的厚层和第三材料层在弱化区域处供应支撑所述薄层的基板。

公开(公告)号：US20070020895A1

公开(公告)日：2007-01-25

申请号：US10558621

申请日：2004-06-03

Applicant: Hubert Moriceau ,  Chrystelle Lagahe ,  Benoit Bataillou

Inventor： Hubert Moriceau ,  Chrystelle Lagahe ,  Benoit Bataillou

IPC: H01L21/04

CPC classification number: H01L21/76254

Abstract: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate at an interface, implantation of gaseous species in the thick layer of first material to create a weakened zone delimiting said thin layer between the interface and the weakened zone, deposit a layer of third material called the self-supporting layer on the thick layer made of first material, fracture within the structure composed of the final substrate, the thick layer of first material and the layer of third material, at the weakened zone to supply the substrate supporting said thin layer.

Abstract translation: 本发明涉及一种获得由第二材料制成的基板上由第一材料制成的薄层的方法，所述第二材料被称为最终基板，包括以下步骤：将第一材料的厚层在其主面之一 在界面处的最终底物，在第一材料的厚层中注入气态物质以产生限定界面和弱化区之间的所述薄层的弱化区，在厚层上沉积称为自支撑层的第三材料层 由第一材料制成，在由最终基底构成的结构内的断裂，第一材料的厚层和第三材料层在弱化区域处供应支撑所述薄层的基板。

公开(公告)号：US20060286770A1

公开(公告)日：2006-12-21

申请号：US11509047

申请日：2006-08-24

Applicant: Bruno Ghyselen ,  Cecile Aulnette ,  Benoit Bataillou ,  Carlos Mazure ,  Hubert Moriceau

Inventor： Bruno Ghyselen ,  Cecile Aulnette ,  Benoit Bataillou ,  Carlos Mazure ,  Hubert Moriceau

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76254 ,  Y10S438/977

Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate. This method includes providing a source substrate with a zone of weakness therein that defines a relatively thick useful layer between the zone of weakness and a front face of the source substrate; bonding the front face of the source substrate to a support substrate and detaching the useful layer from the source substrate at the zone of weakness to transfer the useful layer to the support substrate; implanting atomic species into a free face of the useful layer to a controlled mean implantation depth therein to form a zone of weakness within the useful layer that defines front and rear useful layers, with the rear useful layer contacting the source substrate and the front useful layer containing a greater concentration of defects; bonding a stiffening substrate to the free face of the front useful layer after implantation of the atomic species; and detaching the front useful layer from the rear useful layer along the zone of weakness to form a semiconductor structure comprising the support substrate and the rear useful layer thereon. The structures obtained can be used in the fields of electronics, optoelectronics or optics.

Abstract translation: 一种用于制造半导体结构的方法，所述半导体结构在衬底上包括至少一个有用层。 该方法包括提供源极基底中的弱化区域，其在弱化区域和源极基底的前面之间限定相对较厚的有用层; 将源极基板的正面粘合到支撑基板上，并在弱化区域将有用层与源极基板分离，以将有用层转移到支撑基板; 将原子物质植入有用层的自由面中，以在其中形成受控的平均注入深度，以在限定前后有用层的有用层内形成弱化区，其中后部有用层与源极基底和前部有用层接触 含有较大浓度的缺陷; 在加入原子物质之后将加强基底粘合到前有用层的自由面上; 并且沿着弱化区从后部有用层分离前部有用层，以形成包括支撑基板和其上的后部有用层的半导体结构。 所获得的结构可用于电子学，光电子学或光学领域。

公开(公告)号：US20080063143A1

公开(公告)日：2008-03-13

申请号：US11666368

申请日：2005-10-24

Applicant: Francois Rieutord ,  Hubert Moriceau ,  Benoit Bataillou

Inventor： Francois Rieutord ,  Hubert Moriceau ,  Benoit Bataillou

IPC: G01N23/20

CPC classification number: G01N23/20 ,  G01N19/04

Abstract: The adhesion between two layers, in particular two thin layers of a microelectronic device, is a data item of importance. It was found that the closure ratio of the interface could be used, in non-destructive manner, to determine a measurement of bond energy. A method and a device using a magnitude characteristic of this length are described, in particular using low incidence X-ray reflection and electronic density at the interface.

Abstract translation: 两层之间的粘附，特别是微电子器件的两个薄层，是重要的数据项。 已经发现界面的封闭比可以以非破坏性方式用于确定键能的测量。 具体地说，使用该长度的幅度特性的方法和装置，特别是在界面处使用低入射X射线反射和电子密度。

公开(公告)号：US07688946B2

公开(公告)日：2010-03-30

申请号：US11666368

申请日：2005-10-24

Applicant: Francois Rieutord ,  Hubert Moriceau ,  Benoit Bataillou

Inventor： Francois Rieutord ,  Hubert Moriceau ,  Benoit Bataillou

IPC: G01N23/20

CPC classification number: G01N23/20 ,  G01N19/04

Abstract: The adhesion between two layers, in particular two thin layers of a microelectronic device, is a data item of importance. It was found that the closure ratio of the interface could be used, in non-destructive manner, to determine a measurement of bond energy. A method and a device using a magnitude characteristic of this length are described, in particular using low incidence X-ray reflection and electronic density at the interface.

Abstract translation: 两层之间的粘附，特别是微电子器件的两个薄层，是重要的数据项。 已经发现界面的封闭比可以以非破坏性方式用于确定键能的测量。 具体地说，使用该长度的幅度特性的方法和装置，特别是在界面处使用低入射X射线反射和电子密度。

公开(公告)号：US07115481B2

公开(公告)日：2006-10-03

申请号：US10686084

申请日：2003-10-14

Applicant: Bruno Ghyselen ,  Cécile Aulnette ,  Benoit Bataillou ,  Carlos Mazure ,  Hubert Moriceau

Inventor： Bruno Ghyselen ,  Cécile Aulnette ,  Benoit Bataillou ,  Carlos Mazure ,  Hubert Moriceau

IPC: H01L21/30

CPC classification number: H01L21/76254 ,  Y10S438/977

Abstract: A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.

Abstract translation: 一种用于同时产生至少一对半导体结构的方法，每个半导体结构在衬底上包括至少一个有用层。 该方法包括提供初始结构，其包括在支撑衬底上具有正面的有用层。 将原子物质植入有用层中至受控的平均植入深度，以形成限定第一和第二有用层的有用层内的弱点区域。 接下来，将加强基板粘合到初始结构的正面。 然后沿着弱化区从第二有用层分离第一有用层，以获得一对具有第一结构的半导体结构，该第一结构包括加强衬底和第一有用层，以及包括支撑衬底和第二有用层的第二结构 。 所获得的结构可用于电子学，光电子学或光学领域。

公开(公告)号：US08534914B2

公开(公告)日：2013-09-17

申请号：US12863744

申请日：2009-01-27

Applicant: Viet Nguyen Hoang ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  David Van Steenwinckel

Inventor： Viet Nguyen Hoang ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  David Van Steenwinckel

IPC: H05B33/08 ,  H05B37/02 ,  G01K7/01

CPC classification number: H05B33/0818 ,  G01K7/01 ,  H05B33/0866 ,  H05B33/089

Abstract: A method of estimating the junction temperature of a light emitting diode comprises driving a forward bias current through the diode, the current comprising a square wave which toggles between high and low current values (Ihigh, llow), the high current value (lhigh) comprising an LED operation current, and the low current value (ILOW) comprising a non-zero measurement current. The forward bias voltage drop (Vf) is sampled and the forward bias voltage drop (Vflow) is determined at the measurement current (ILOW)—The temperature is derived from the determined forward bias voltage drop.

Abstract translation: 估计发光二极管的结温的方法包括驱动通过二极管的正向偏置电流，该电流包括在高电流值和低电流值（Ihigh，llow）之间切换的方波，高电流值（lhigh）包括 LED操作电流和包括非零测量电流的低电流值（ILOW）。 正向偏置电压降（Vf）被采样，并且在测量电流（ILOW）下确定正向偏置电压降（Vflow） - 温度是从确定的正向偏压电压降导出的。

公开(公告)号：US08217558B2

公开(公告)日：2012-07-10

申请号：US12910583

申请日：2010-10-22

Applicant: Pascal Bancken ,  Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou ,  David van Steenwinckel

Inventor： Pascal Bancken ,  Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou ,  David van Steenwinckel

IPC: H01J7/24 ,  H01L33/00

CPC classification number: H01L33/642 ,  F21V29/70 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/486 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatus for regulating the temperature of a light emitting diode (LED). The apparatus includes a heat sink, an LED mount, and an LED mounted on the LED mount. The LED mount is configured to change shape in response to a change in temperature. The change in shape alters the position of the LED relative to the heat sink, for adjusting heat transfer between the LED and the heat sink. The LED mount may include a laminated portion such as a bi-metallic strip.

Abstract translation: 用于调节发光二极管（LED）的温度的装置。 该装置包括散热器，LED安装座和安装在LED安装座上的LED。 LED安装座被配置为响应于温度变化而改变形状。 形状的变化会改变LED相对于散热片的位置，以调节LED和散热片之间的热传递。 LED支架可以包括诸如双金属条的层压部分。

公开(公告)号：US20120001570A1

公开(公告)日：2012-01-05

申请号：US13257266

申请日：2010-02-25

Applicant: Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

Inventor： Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

IPC: H05B37/02

CPC classification number: H05B33/086 ,  H05B33/0815 ,  H05B33/0848

Abstract: A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED whilst the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilise the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.

Abstract translation: 公开了一种控制LED的方法，包括第一次用DC电流驱动LED，第二次中断DC电流，使得第一时间和第二时间总和到一个周期，确定至少一个特性 所述LED在DC电流中断期间，并且根据所述至少一个特性在随后的时段期间控制所述DC电流。 因此，本发明由于DC操作的简单性而受益。 通过在DC模式下操作LED，而不是在PWM模式下说明，可以避免能够调整占空比的要求。 通过包含直流电流的中断，可以利用LED本身作为传感器，以便确定LED的特性。 从而避免了对附加传感器的需要。

公开(公告)号：US08368105B2

公开(公告)日：2013-02-05

申请号：US12922072

申请日：2009-03-09

Applicant: Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

Inventor： Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

IPC: H01L33/00

CPC classification number: H01L27/14625 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/14685

Abstract: The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate (10) comprising a pixelated element (12) and a light path (38) to the pixelated element (12). The IC comprises a first dielectric layer (14) covering the substrate (10) but not the pixilated element (12), a first metal layer (16) covering a part of the first dielectric layer (14), a second dielectric layer (18) covering a further part of first dielectric layer (14), a second metal layer (20) covering a part of the second dielectric layer (18) and extending over the pixelated element (12) and a part of the first metal layer (16), the first metal layer (16) and the second metal layer (20) forming an air-filled light path (38) to the pixelated element (12). The air-filled light path (38) is formed by creation of holes in the first dielectric layer (14) and the second dielectric layer (18), filling the holes with sacrificial materials, and removal of the sacrificial materials after deposition and patterning of the second metal layer (20). This yields an IC having a low-loss light path to the pixelated element (12). The light path may act as a color filter, e.g. a Fabry-Perot color filter.

Abstract translation: 本发明涉及一种集成电路（IC）的制造方法，该集成电路（IC）包括基板（10），该基板（10）包括像素化元件（12）和到像素化元件（12）的光路（38）。 所述IC包括覆盖所述衬底（10）而不是所述像素化元件（12）的第一介电层（14），覆盖所述第一介电层（14）的一部分的第一金属层（16），第二介电层（18） ）覆盖第一介电层（14）的另一部分，覆盖第二介电层（18）的一部分并在像素化元件（12）上延伸的第二金属层（20）和第一金属层（16）的一部分 ），第一金属层（16）和第二金属层（20）形成到像素化元件（12）的充气光路（38）。 充气光路（38）通过在第一电介质层（14）和第二电介质层（18）中产生孔而形成，用牺牲材料填充孔，并且在沉积和图案化之后去除牺牲材料 第二金属层（20）。 这产生具有到像素化元件（12）的低损耗光路的IC。 光路可以用作滤色器，例如， 法布里 - 珀罗滤镜。