公开(公告)号：US20160315164A1

公开(公告)日：2016-10-27

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

摘要翻译： 提供半导体器件。 半导体器件包括绝缘层。 半导体器件包括在绝缘层上的稀土元素供给层。 此外，半导体器件包括在稀土元素供给层上的金属层。 稀土元素供给层位于绝缘层与金属层之间。 还提供了形成半导体器件的方法。

公开(公告)号：US09793368B2

公开(公告)日：2017-10-17

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US09923077B2

公开(公告)日：2018-03-20

申请号：US15093896

申请日：2016-04-08

申请人： Yoon-tae Hwang ,  Ki-joong Yoon ,  Moon-kyu Park ,  Sang-jin Hyun ,  Hoon-joo Na

发明人： Yoon-tae Hwang ,  Ki-joong Yoon ,  Moon-kyu Park ,  Sang-jin Hyun ,  Hoon-joo Na

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L21/28176 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/78

摘要： A method of curing a dielectric layer, such as a dielectric layer that has a relatively small thickness and/or a narrow width or a complicated shape, is provided. The method of curing a dielectric layer for the manufacture of a semiconductor device includes providing the dielectric layer, wherein the dielectric layer is on a semiconductor layer; forming a first metal-containing layer on the dielectric layer; forming a curing atom screening region in an upper portion of the first metal-containing layer by injecting screening atoms onto an upper surface of the first metal-containing layer; injecting curing atoms into the first metal-containing layer through the upper surface of the first metal-containing layer; and flowing the curing atoms into the dielectric layer in an atmosphere at a first temperature.

公开(公告)号：US20160307762A1

公开(公告)日：2016-10-20

申请号：US15093896

申请日：2016-04-08

申请人： Yoon-tae Hwang ,  Ki-joong Yoon ,  Moon-kyu Park ,  Sang-jin Hyun ,  Hoon-joo Na

发明人： Yoon-tae Hwang ,  Ki-joong Yoon ,  Moon-kyu Park ,  Sang-jin Hyun ,  Hoon-joo Na

IPC分类号： H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02

CPC分类号： H01L29/513 ,  H01L21/28176 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/78

摘要： A method of curing a dielectric layer, such as a dielectric layer that has a relatively small thickness and/or a narrow width or a complicated shape, is provided. The method of curing a dielectric layer for the manufacture of a semiconductor device includes providing the dielectric layer, wherein the dielectric layer is on a semiconductor layer; forming a first metal-containing layer on the dielectric layer; forming a curing atom screening region in an upper portion of the first metal-containing layer by injecting screening atoms onto an upper surface of the first metal-containing layer; injecting curing atoms into the first metal-containing layer through the upper surface of the first metal-containing layer; and flowing the curing atoms into the dielectric layer in an atmosphere at a first temperature.

摘要翻译： 提供固化电介质层的方法，例如具有相对较小厚度和/或窄宽度或复杂形状的电介质层。 固化用于制造半导体器件的电介质层的方法包括提供介电层，其中介电层在半导体层上; 在介电层上形成第一含金属层; 通过将筛选原子注入第一含金属层的上表面，在第一含金属层的上部形成固化原子筛选区; 通过第一含金属层的上表面将固化原子注入第一含金属层; 并在第一温度的气氛中将固化原子流入电介质层。

公开(公告)号：US20160308012A1

公开(公告)日：2016-10-20

申请号：US15059673

申请日：2016-03-03

申请人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

发明人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

摘要翻译： 在包括具有相对窄的宽度和相对较小的间距的栅极线的半导体器件和制造该半导体器件的方法中，所述半导体器件包括具有鳍式有源区的衬底，覆盖上表面的栅极绝缘层 翅片型有源区的侧面以及覆盖翅片型有源区的上表面和两侧的鳍型有源区延伸并相交的栅极线，栅极线位于栅极绝缘层上 其特征在于，所述栅极线的上表面的与所述栅极线的延伸方向垂直的截面的中心部分具有凹形。

公开(公告)号：US09786761B2

公开(公告)日：2017-10-10

申请号：US14955205

申请日：2015-12-01

申请人： Dong-soo Lee ,  Hu-yong Lee ,  Won-keun Chung ,  Hoon-joo Na ,  Taek-soo Jeon ,  Sang-jin Hyun

发明人： Dong-soo Lee ,  Hu-yong Lee ,  Won-keun Chung ,  Hoon-joo Na ,  Taek-soo Jeon ,  Sang-jin Hyun

IPC分类号： B82Y10/00 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/512 ,  B82Y10/00 ,  H01L21/28185 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785

摘要： An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

公开(公告)号：US20110223758A1

公开(公告)日：2011-09-15

申请号：US13116045

申请日：2011-05-26

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US08932922B2

公开(公告)日：2015-01-13

申请号：US13116045

申请日：2011-05-26

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US08293599B2

公开(公告)日：2012-10-23

申请号：US12540090

申请日：2009-08-12

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.

摘要翻译： 具有不同工作功能的双栅极的半导体器件通过使用选择性氮化简单地形成。 在包括第一区域和第二区域的半导体衬底上形成栅极绝缘层，在其上形成具有不同阈值电压的器件。 扩散抑制材料被选择性地注入到第一区域和第二区域之一中的栅极绝缘层中。 在栅极绝缘层上形成扩散层。 工作功能控制材料通过热处理从扩散层直接扩散到栅极绝缘层，其中栅极绝缘层由选择性注入的扩散抑制材料自对准封盖，使得功函数控制材料扩散到 第一个地区和第二个地区的其他地区。 通过去除扩散层，完全暴露栅极绝缘层。 在暴露的栅极绝缘层上形成栅极电极层。 通过蚀刻栅极电极层和栅极绝缘层，分别在第一区域和第二区域中形成具有不同功函数的第一栅极和第二栅极。

公开(公告)号：US20100203716A1

公开(公告)日：2010-08-12

申请号：US12580302

申请日：2009-10-16

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。