公开(公告)号：US20160308012A1

公开(公告)日：2016-10-20

申请号：US15059673

申请日：2016-03-03

申请人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

发明人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

摘要翻译： 在包括具有相对窄的宽度和相对较小的间距的栅极线的半导体器件和制造该半导体器件的方法中，所述半导体器件包括具有鳍式有源区的衬底，覆盖上表面的栅极绝缘层 翅片型有源区的侧面以及覆盖翅片型有源区的上表面和两侧的鳍型有源区延伸并相交的栅极线，栅极线位于栅极绝缘层上 其特征在于，所述栅极线的上表面的与所述栅极线的延伸方向垂直的截面的中心部分具有凹形。

公开(公告)号：US20160315164A1

公开(公告)日：2016-10-27

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

摘要翻译： 提供半导体器件。 半导体器件包括绝缘层。 半导体器件包括在绝缘层上的稀土元素供给层。 此外，半导体器件包括在稀土元素供给层上的金属层。 稀土元素供给层位于绝缘层与金属层之间。 还提供了形成半导体器件的方法。

公开(公告)号：US09793368B2

公开(公告)日：2017-10-17

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US07700454B2

公开(公告)日：2010-04-20

申请号：US11462178

申请日：2006-08-03

申请人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

发明人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

IPC分类号： H01L21/20

CPC分类号： H01L28/84 ,  H01L27/1085

摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

摘要翻译： 提供一种制造均匀起皱的电容器下电极而不需要进行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。 形成第一导电层。 然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。 接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。 由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。 然后可以形成电介质层和上电容器电极。

公开(公告)号：US07034350B2

公开(公告)日：2006-04-25

申请号：US10795020

申请日：2004-03-05

申请人： Suk-jin Chung ,  Wan-don Kim ,  Cha-young Yoo ,  Kwang-hee Lee ,  Han-jin Lim ,  Jin-il Lee

发明人： Suk-jin Chung ,  Wan-don Kim ,  Cha-young Yoo ,  Kwang-hee Lee ,  Han-jin Lim ,  Jin-il Lee

IPC分类号： H01L27/108

CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L28/91

摘要： Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.

摘要翻译： 电容器包括集成电路（半导体）基板和布置在集成电路基板上并且在其中包括金属插塞的层间电介质。 下部电极设置在层间电介质上并接触金属插塞。 下电极在其中包括空腔，并且在腔中包括掩埋层。 掩埋层是吸氧材料。 设置在下电极上的电介质层和上电极设置在电介质层上。 下电极可以是贵金属层。 当初始形成时，掩埋层可以填充空腔并且可以不含有氧（O 2 2 N）。

公开(公告)号：US06893501B2

公开(公告)日：2005-05-17

申请号：US10320407

申请日：2002-12-17

申请人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

发明人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  C30B25/04

CPC分类号： H01L28/57 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/1085 ,  H01L28/65

摘要： A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

摘要翻译： 一种覆盖半导体存储器件的电容器，优选金属 - 绝缘体 - 金属（MIM）电容器的覆盖层的方法，其中所述方法包括在半导体上形成具有下电极，电介质层和上电极的电容器 衬底，在电容器上形成覆盖层，并使介电层结晶。 这里，形成覆盖层包括在不提供氧气的情况下沉积封盖层的稳定性，通过为封盖层提供反应源沉积覆盖层; 并且清洗用于形成覆盖层的反应器的内部。

公开(公告)号：US08859383B2

公开(公告)日：2014-10-14

申请号：US13424825

申请日：2012-03-20

申请人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

发明人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/31683 ,  H01L21/318 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

摘要翻译： 一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层 下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

公开(公告)号：US20090072350A1

公开(公告)日：2009-03-19

申请号：US12270286

申请日：2008-11-13

申请人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

发明人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

IPC分类号： H01L29/92 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/60

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括形成在支撑层上并具有接触孔的绝缘层。 第一接触塞形成在接触孔的内壁和底部上。 第二接触插塞将接触孔埋入并形成在第一接触插塞上。 导电层连接到第一接触插塞和第二接触插塞。 形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

公开(公告)号：US20060148193A1

公开(公告)日：2006-07-06

申请号：US11374349

申请日：2006-03-13

申请人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-Jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

发明人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-Jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

IPC分类号： H01L21/44

CPC分类号： C23C16/18 ,  H01L21/28556 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).

摘要翻译： 提供1）一种在单一工艺条件下形成钌膜的方法，由此保持钌膜对下层的高附着性，以及2）使用这种方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法 钌膜成型方法。 形成钌膜的方法包括以0.2-1ccm的流速和20-60sccm的流量的氧供给双（异庚烷-2,4-二酮）降冰片二烯钌，并将钌膜以 在0.5-5乇的压力下使用化学气相沉积（CVD）来制备330-430℃。

公开(公告)号：US20050161727A1

公开(公告)日：2005-07-28

申请号：US11083874

申请日：2005-03-18

申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。