公开(公告)号：US07868438B2

公开(公告)日：2011-01-11

申请号：US12238894

申请日：2008-09-26

Applicant: Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

Inventor： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

IPC: H01L23/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US20070040280A1

公开(公告)日：2007-02-22

申请号：US11589192

申请日：2006-10-30

Applicant: Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

Inventor： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

IPC: H01L23/52

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US06751132B2

公开(公告)日：2004-06-15

申请号：US10108240

申请日：2002-03-26

Applicant: Hyun-Soon Jang ,  Jae-Hoon Kim

Inventor： Hyun-Soon Jang ,  Jae-Hoon Kim

IPC: G11C700

CPC classification number: G11C5/146

Abstract: A semiconductor memory device which provides an improved operation performance in response to a relatively low external power voltage is included. The device comprises a plurality of direct-current voltage generating circuits for generating a plurality of direct-current voltages and a plurality of reference voltage generating circuits for generating reference voltages for the plurality of the direct-current voltage generating circuits, respectively.

Abstract translation: 包括提供响应于相对较低的外部电源电压的改进的操作性能的半导体存储器件。 该装置包括用于产生多个直流电压的多个直流电压产生电路和用于分别产生多个直流电压产生电路的参考电压的多个参考电压发生电路。

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US06819617B2

公开(公告)日：2004-11-16

申请号：US10452176

申请日：2003-06-02

Applicant: Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

Inventor： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC: G11C700

CPC classification number: G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract translation: 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个部分（例如，1 / 2,1 / 8或{分数（1/16））的一部分执行用于对存储数据进行再充电的刷新操作 在一个方面，通过（1）在自刷新操作期间通过行地址计数器控制行地址的生成来执行PASR操作，以及（2）控制自身的自身 - 刷新周期产生电路，用于调整其自刷新周期输出，在PASR操作期间以减少电流消耗的方式调整自刷新周期，另一方面，通过控制一个PASR操作来执行PASR操作 或更多行对应于自刷新操作期间的部分单元阵列的行地址，从而通过阻止存储器组的未使用块的激活来实现自刷新电流消耗的减少。

公开(公告)号：US5771200A

公开(公告)日：1998-06-23

申请号：US771776

申请日：1996-12-20

Applicant: Il-Jae Cho ,  Hyun-Soon Jang

Inventor： Il-Jae Cho ,  Hyun-Soon Jang

IPC: G11C11/41 ,  G11C5/02 ,  G11C7/10 ,  G11C11/40 ,  G11C11/401 ,  G11C8/00 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C5/025 ,  G11C7/10

Abstract: A semiconductor memory device reduces the distance occupied between a data path circuit and pads, and minimizes the length of data lines and main input/output lines, thereby improving an operating speed thereof. The semiconductor memory device includes a memory array divided into four array blocks which are independently arranged; a plurality of pads disposed in an area between the upper array blocks and the respective lower array blocks; a data path control circuit disposed in an area between the left array blocks and the respective right array blocks; a data path circuit disposed in a middle center area among the four array blocks; a plurality of data lines connecting the pads to the data path circuit; and a plurality of main input/output lines connecting the memory array to the data path circuit. In this configuration, a distance between the data lines and the main input/output lines and the data path circuit can be minimized.

Abstract translation: 半导体存储器件减少了数据路径电路和焊盘之间的距离，并且使数据线和主输入/输出线的长度最小化，从而提高了其工作速度。 半导体存储器件包括分成独立布置的四个阵列块的存储器阵列; 设置在上阵列块和相应的下阵列块之间的区域中的多个焊盘; 数据路径控制电路，设置在左阵列块和各个右阵列块之间的区域中; 设置在所述四个阵列块中的中央区域的数据路径电路; 将所述焊盘连接到所述数据路径电路的多条数据线; 以及将存储器阵列连接到数据路径电路的多个主输入/输出线。 在这种配置中，数据线与主输入/输出线和数据路径电路之间的距离可以最小化。

公开(公告)号：US5646899A

公开(公告)日：1997-07-08

申请号：US575714

申请日：1995-12-20

Applicant: Hyun-Soon Jang ,  Seung-Hun Lee

Inventor： Hyun-Soon Jang ,  Seung-Hun Lee

IPC: G11C11/409 ,  G11C7/06 ,  G11C7/22 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/065

Abstract: A bit line sensing circuit of a semiconductor memory device is disclosed which includes a pull-up control signal generator that enables the peak current to be small by supplying to the P sense amplifier a pull-up voltage of the low level in an initial sensing process. When the peak current is stabilized, the pull-up control signal generator then reduces the time required for raising the pull-up voltage by very quickly raising the voltage of the pull-up control signal. This results in the advantages that the peak current can be greatly reduced without slowing sensing speed, and voltage noise caused from peak currents can be eliminated.

Abstract translation: 公开了一种半导体存储器件的位线感测电路，其包括上拉控制信号发生器，其通过在初始感测过程中向P读出放大器提供低电平的上拉电压来使峰值电流变小 。 当峰值电流稳定时，上拉控制信号发生器通过非常快速地提高上拉控制信号的电压来减少提高上拉电压所需的时间。 这导致了峰值电流可以大大降低而不减慢感测速度的优点，并且可以消除由峰值电流引起的电压噪声。

公开(公告)号：US5568445A

公开(公告)日：1996-10-22

申请号：US397690

申请日：1995-03-02

Applicant: Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

Inventor： Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

IPC: G11C11/407 ,  G11C7/00 ,  G11C7/22 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C7/22

Abstract: A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

Abstract translation: 一种用于与从外部施加的系统时钟同步地处理数据的半导体存储器件包括用于产生写等待时间控制信号的电路，用于根据响应于列产生的多个有效信息信号产生一个有源信息放大信号的电路 以及用于保持列地址计数器，脉冲串长度计数器和数据传输切换电路的内部操作的电路，其中有效信息放大信号处于活动状态的规定时间。

公开(公告)号：US5337277A

公开(公告)日：1994-08-09

申请号：US942450

申请日：1992-09-09

Applicant: Hyun-Soon Jang

Inventor： Hyun-Soon Jang

IPC: G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C29/808

Abstract: A row redundancy circuit for repairing a defective cell of a memory cell array in a semiconductor memory device comprising an address selector 300 for receiving two or more of address bit pairs, of an address bit pair group, designating the defective cell to selectively output one of the two or more address bit pairs, a fuse box 100 for storing the information of the remaining address bits of the address bit pair group, except the address bits of the selected address bit pair output by the address selector, and at least a redundant decoder 200, 200A for decoding the output signals of the address selector and fuse box, thereby maximizing the row redundancy efficiency.

Abstract translation: 一种用于修复半导体存储器件中的存储单元阵列的有缺陷单元的行冗余电路，包括地址选择器300，用于接收地址位对组中的两个或更多个地址位对，指定有缺陷单元以选择性地输出 两个或多个地址位对，用于存储地址位对组的剩余地址位的信息的保险丝盒100，除了由地址选择器输出的所选择的地址位对的地址位以及至少一个冗余解码器 200,200A，用于解码地址选择器和熔丝盒的输出信号，从而最大化行冗余效率。

公开(公告)号：US20090044063A1

公开(公告)日：2009-02-12

申请号：US11974342

申请日：2007-10-12

Applicant: Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

Inventor： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

Abstract translation: 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。