公开(公告)号：US20140246765A1

公开(公告)日：2014-09-04

申请号：US14277226

申请日：2014-05-14

Applicant: IBIDEN CO., LTD.

Inventor： Naoto ISHIDA ,  Takema Adachi

IPC: H01L23/495 ,  H05K1/02

CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract translation: 印刷电路板包括芯基板，容纳在基板中的电子部件，层叠在基板的第一表面上的第一累积层，并且包括最外层间树脂绝缘层和最外层导体层，最外层导体层形成在最外层的层间树脂绝缘层上 第一累积层和层叠在基板的第二表面上的第二堆积层，并且包括形成在第二堆积层的最外层间树脂绝缘层上的最外层间树脂绝缘层和最外导电层。 第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于第二堆积层的最外层间树脂绝缘层的热膨胀系数。

公开(公告)号：US20140026412A1

公开(公告)日：2014-01-30

申请号：US13948642

申请日：2013-07-23

Applicant: IBIDEN Co., Ltd.

Inventor： Naoto ISHIDA

IPC: H05K3/40 ,  H05K3/10

CPC classification number: H05K3/4038 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/10 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for manufacturing a printed wiring board includes forming on a support sheet an intermediate body including a first insulation layer, a second insulation layer and a first conductive layer interposed between the first insulation layer and the second insulation layer, and separating the support sheet from the intermediate body including the insulation layer, the first conductive layer and the second insulation layer such that the intermediate body is detached from the support sheet.

Abstract translation: 一种制造印刷电路板的方法，包括在支撑片上形成中间体，该中间体包括第一绝缘层，第二绝缘层和介于第一绝缘层和第二绝缘层之间的第一导电层，并将支撑片从 所述中间体包括所述绝缘层，所述第一导电层和所述第二绝缘层，使得所述中间体与所述支撑片分离。

公开(公告)号：US20140262447A1

公开(公告)日：2014-09-18

申请号：US14210802

申请日：2014-03-14

Applicant: IBIDEN CO., LTD.

Inventor： Naoki KATSUDA ,  Naoto ISHIDA ,  Kota NODA ,  Nobuhisa KURODA

IPC: H05K1/02

CPC classification number: H05K1/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/094

Abstract: A multilayer printed wiring board for mounting a semiconductor element includes a core substrate, a first laminated structure on first surface of the substrate and including a conductive circuit layer on the first surface of the substrate, a resin insulating layer and the outermost conductive circuit layer, and a second laminated structure on second surface of the substrate and including a conductive circuit layer on the second surface of the substrate, a resin insulating layer and the outermost conductive circuit layer. The outermost conductive layer in the first structure has solder pads positioned to mount a semiconductor element and solder bumps formed on the pads, respectively, the outermost conductive layer in the second structure has solder pads positioned to mount a wiring board, and the outermost conductive layers in the first and second structures have thicknesses formed greater than thicknesses of the conductive layers on the surfaces of the substrate.

Abstract translation: 用于安装半导体元件的多层印刷线路板包括芯基板，在基板的第一表面上的第一层叠结构，并且在基板的第一表面上包括导电电路层，树脂绝缘层和最外导体电路层， 以及在所述基板的第二表面上的第二层叠结构，并且在所述基板的第二表面上包括导电电路层，树脂绝缘层和最外面的导电电路层。 第一结构中的最外面的导电层具有分别安装半导体元件和形成在焊盘上的焊锡凸块的焊盘，第二结构中的最外面的导电层具有定位成安装布线板的焊盘，并且最外面的导电层 在第一和第二结构中，厚度大于衬底表面上的导电层的厚度。

公开(公告)号：US20130240258A1

公开(公告)日：2013-09-19

申请号：US13836123

申请日：2013-03-15

Applicant: IBIDEN CO., LTD.

Inventor： Naoto ISHIDA ,  Takema ADACHI

IPC: H05K1/03

CPC classification number: H05K1/0306 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/185 ,  H05K3/4673 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate including an insulative substrate, a first conductive layer formed on first surface of the insulative substrate, and a second conductive layer formed on second surface of the insulative substrate, a first buildup laminated on first surface of the core and including an interlayer insulation layer, a conductive layer formed on the insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer, and a second buildup laminated on second surface of the core and including an interlayer insulation layer, a conductive layer formed on the interlayer insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer. The insulation layer of the first buildup has thermal expansion coefficient set higher than thermal expansion coefficient of the insulation layer of the second buildup.

Abstract translation: 印刷电路板包括具有绝缘基板的芯基板，形成在绝缘基板的第一面上的第一导电层和形成在绝缘基板的第二面上的第二导电层，层叠在芯的第一面上的第一积层 并且包括层间绝缘层，形成在所述绝缘层上的导电层和穿过所述绝缘层并连接到所述导电层的通孔导体，以及层叠在所述芯的第二表面上并包括层间绝缘层的第二堆积层， 形成在层间绝缘层上的导电层和穿过绝缘层并连接到导电层的通孔导体。 第一次堆积的绝缘层的热膨胀系数设定为高于第二次堆积的绝缘层的热膨胀系数。

公开(公告)号：US20130221518A1

公开(公告)日：2013-08-29

申请号：US13690570

申请日：2012-11-30

Applicant: IBIDEN CO., LTD.

Inventor： Naoto ISHIDA ,  Takema ADACHI

IPC: H05K1/02 ,  H01L23/498

CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate, a first buildup layer laminated on a first surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on a second surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost conductive layer of the first buildup layer includes pads positioned to mount a semiconductor device on a surface of the first buildup layer, and the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract translation: 印刷电路板包括芯基板，层叠在芯基板的第一表面上并且包括最外层间树脂绝缘层的第一累积层和形成在第一堆积层的最外层间树脂绝缘层上的最外导电层，以及 层叠在所述芯基板的第二表面上并且包括最外层间树脂绝缘层和形成在所述第二堆积层的最外层间树脂绝缘层上的最外导体层的第二堆积层。 第一累积层的最外面的导电层包括定位成将半导体器件安装在第一堆积层的表面上的焊盘，第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于热 第二堆积层的最外层间树脂绝缘层的膨胀系数。