公开(公告)号：US11617262B2

公开(公告)日：2023-03-28

申请号：US17588414

申请日：2022-01-31

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Daisuke Minoura

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/38

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.

公开(公告)号：US10477699B2

公开(公告)日：2019-11-12

申请号：US15447705

申请日：2017-03-02

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Masaaki Murase ,  Takayuki Katsuno

IPC: H05K3/30 ,  H05K3/34 ,  H05K3/46 ,  H05K3/22 ,  H05K1/11 ,  H05K1/18

Abstract: A method for manufacturing an electronic component attached board includes preparing a first support plate, forming aggregate wiring boards on the first plate such that the aggregate boards each including wiring board side by side are formed in connected state on surface of the first plate, separating the first plate from the aggregate boards, dividing the aggregate boards into individual aggregate boards each including the wiring boards, bonding a second support plate to surface of each individual aggregate board such that each individual aggregate board is bonded to surface of the second plate, mounting electronic components on the wiring boards on the second plate such that each wiring board has an electronic component thereon, dividing the wiring boards into individual wiring boards, and separating the second plate from the individual wiring board. The surface of the first plate has size larger than size of the surface of the second plate.

公开(公告)号：US10231369B2

公开(公告)日：2019-03-12

申请号：US15783053

申请日：2017-10-13

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Takema Adachi ,  Hidetoshi Noguchi ,  Shota Tachibana

IPC: H05K9/00 ,  B32B37/02 ,  B32B37/14 ,  B29C70/88

Abstract: A shield cap for protecting an electronic component includes a cap member having a side wall portion and a ceiling portion, a conductive film formed on the cap member such that the conductive film is formed to shield electromagnetic waves, and a metal layer formed on a portion of the side wall portion such that the metal layer is interposed between the conductive film and the portion of the side wall portion. The side wall and ceiling portions are forming an accommodation space to accommodate an electronic component, and the metal layer is formed on a surface of the side wall portion on the opposite side of a surface of the side wall portion facing the ceiling portion and interposed between the conductive film and the side wall portion.

公开(公告)号：US09980371B2

公开(公告)日：2018-05-22

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H05K3/02 ,  H05K3/18

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

公开(公告)号：US20230113278A1

公开(公告)日：2023-04-13

申请号：US17936924

申请日：2022-09-30

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Yuji Ikawa

IPC: H05K3/00 ,  H05K3/10 ,  H05K3/26 ,  H05K1/03

Abstract: A method for manufacturing a wiring substrate includes forming a second resin insulating layer on a first resin insulating layer such that the second resin insulating layer is in contact with a surface of the first resin insulating layer, irradiating laser upon the second resin insulating layer such that a recess penetrating through the second resin insulating layer and exposing the first resin insulating layer is formed, and forming a conductor layer including conductor material filled in the recess formed through the second resin insulating layer such that the conductor layer is embedded in the second resin insulating layer. The second resin insulating layer are formed on the surface of the first resin insulating layer such that the first resin insulating layer and the second resin insulating layer have different processability with respect to the laser.

公开(公告)号：US10440823B2

公开(公告)日：2019-10-08

申请号：US16245396

申请日：2019-01-11

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40

Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each often-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).

公开(公告)号：US10194569B2

公开(公告)日：2019-01-29

申请号：US15782275

申请日：2017-10-12

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Takema Adachi ,  Hidetoshi Noguchi ,  Shota Tachibana

IPC: H05K9/00 ,  H05K13/00 ,  H05K5/06

Abstract: A shield cap for protecting an electronic component includes a cap member having a side wall portion and a ceiling portion, and a conductive film formed on the cap member such that the conductive film is formed to shield electromagnetic waves. The ceiling portion includes a resin material and a reinforcing material, and the cap member is formed such that the side wall portion and the ceiling portion are forming an accommodation space to accommodate an electronic component.

公开(公告)号：US20180270951A1

公开(公告)日：2018-09-20

申请号：US15920594

申请日：2018-03-14

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/18 ,  H05K3/06 ,  H05K3/24

CPC classification number: H05K1/113 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0373 ,  H05K3/061 ,  H05K3/14 ,  H05K3/18 ,  H05K3/24 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09827 ,  H05K2203/0152 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/107

Abstract: A printed wiring board includes a first conductor layer forming an inner conductor layer, a second conductor layer forming a first outemiost conductor layer, a third conductor layer forming a second outermost conductor layer, insulating layers including first and second insulating layers, first via conductors connecting the first and second conductor layers, and second via conductors connecting the first and third conductor layers. The first conductor layer has thickness greater than thicknesses of the second and third conductor layers, the second conductor layer includes component mounting pads positioned to mount an electronic component on the second conductor layer and extending outside component mounting region corresponding to projection region of the component, and the first via conductors include a first set of the first via conductors formed directly underneath the component mounting region and a second set of the first via conductors formed on outer side of the component mounting region.

公开(公告)号：US20160295692A1

公开(公告)日：2016-10-06

申请号：US15084165

申请日：2016-03-29

Applicant: IBIDEN CO., LTD.

Inventor： Koji ASANO ,  Takema Adachi

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K3/4688 ,  H05K1/113 ,  H05K3/4652 ,  H05K2201/09045 ,  H05K2201/09127 ,  H05K2203/308

Abstract: A printed wiring board includes a core substrate, and a first build-up wiring layer formed on the core substrate and including a wiring layer such that the wiring layer includes a resin insulating layer and a conductor layer laminated on the resin insulating layer. The first build-up wiring layer is formed on a first surface of the core substrate such that the first build-up wiring layer forms a high-rise region and a low-rise region with respect to a lamination direction, the first build-up wiring layer includes electrodes positioned to connect an electronic component to the first build-up wiring layer, and the first build-up wiring layer is formed such that the low-rise region is extending in two or more directions from the high-rise region to edges of the core substrate.

Abstract translation: 印刷电路板包括芯基板和形成在芯基板上并且包括布线层的第一堆叠布线层，使得布线层包括层压在树脂绝缘层上的树脂绝缘层和导体层。 第一积层布线层形成在芯基板的第一表面上，使得第一堆积布线层相对于层叠方向形成高层区域和低层区域，第一堆积层 布线层包括定位成将电子部件连接到第一叠层布线层的电极，并且形成第一堆积布线层，使得低层区域从高层区域向两个或更多个方向延伸， 芯基板的边缘。

公开(公告)号：US20140246765A1

公开(公告)日：2014-09-04

申请号：US14277226

申请日：2014-05-14

Applicant: IBIDEN CO., LTD.

Inventor： Naoto ISHIDA ,  Takema Adachi

IPC: H01L23/495 ,  H05K1/02

CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract translation: 印刷电路板包括芯基板，容纳在基板中的电子部件，层叠在基板的第一表面上的第一累积层，并且包括最外层间树脂绝缘层和最外层导体层，最外层导体层形成在最外层的层间树脂绝缘层上 第一累积层和层叠在基板的第二表面上的第二堆积层，并且包括形成在第二堆积层的最外层间树脂绝缘层上的最外层间树脂绝缘层和最外导电层。 第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于第二堆积层的最外层间树脂绝缘层的热膨胀系数。