公开(公告)号：US10070537B2

公开(公告)日：2018-09-04

申请号：US15065620

申请日：2016-03-09

Applicant: INTEL CORPORATION

Inventor： Deepak Arora ,  Daniel N. Sobieski ,  Dilan Seneviratne ,  Ebrahim Andideh ,  James C. Meyer

IPC: B32B38/10 ,  H05K3/46 ,  C23C14/22 ,  H05K3/42 ,  H05K3/10 ,  H01L21/48 ,  B32B43/00 ,  H01L21/44 ,  H05K3/00 ,  H05K3/28 ,  H01L21/56

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

公开(公告)号：US09554468B2

公开(公告)日：2017-01-24

申请号：US14227697

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Ching-Ping Janet Shen ,  Charan K. Gurumurthy ,  Dilan Seneviratne ,  Ravi Shankar ,  Liwen Jin ,  Deepak Arora

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/46 ,  B32B3/26 ,  B32B15/20 ,  B32B37/12 ,  B32B7/12 ,  B32B15/08 ,  B32B37/10 ,  H05K3/28 ,  H01L23/13 ,  H01L23/538

CPC classification number: H05K1/183 ,  B32B3/263 ,  B32B7/12 ,  B32B15/08 ,  B32B15/20 ,  B32B37/10 ,  B32B37/1284 ,  B32B2307/202 ,  B32B2457/08 ,  H01L23/13 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/185 ,  H05K3/284 ,  Y10T428/24612 ,  Y10T428/2495 ,  Y10T428/31678 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a base, situating an adhesive layer on the inner foil, such that the inner foil is substantially flush with a periphery of the base, situating an outer conductive foil on the adhesive layer, or covering an interface between the adhesive layer, the inner foil and the outer conductive foil with a protective material.

Abstract translation: 本文通常讨论的是可以包括可释放的核心面板的系统和装置。 本公开还包括制造和使用系统和装置的技术。 根据一个实例，制造可释放的芯板的技术可以包括将内箔连接到基底上，将粘合剂层定位在内箔上，使得内箔基本上与基底的周边齐平，将外导电 或者利用保护材料覆盖粘合层，内箔和外导电箔之间的界面。

公开(公告)号：US20160192508A1

公开(公告)日：2016-06-30

申请号：US15065620

申请日：2016-03-09

Applicant: INTEL CORPORATION

Inventor： Deepak Arora ,  Daniel N. Sobieski ,  Dilan Seneviratne ,  Ebrahim Andideh ,  James C. Meyer

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/42 ,  C23C14/22 ,  C23C14/34

CPC classification number: H05K3/4644 ,  B32B38/10 ,  B32B43/006 ,  C23C14/228 ,  H01L21/44 ,  H01L21/48 ,  H01L21/565 ,  H05K3/0014 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/107 ,  H05K3/281 ,  H05K3/42 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1152 ,  Y10T156/1168 ,  Y10T156/1978

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于形成具有光滑表面的电介质的技术和配置。 在一个实施例中，一种方法包括提供具有第一表面和第二表面的电介质，形成在第一表面上的导电特征，以及施加到第二表面的层压板，在层压体保持施加时固化第二表面，以及去除层压体。 可以描述和/或要求保护其他实施例。