公开(公告)号：US09658978B2

公开(公告)日：2017-05-23

申请号：US14209184

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Robert P. Adler

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/364 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0026

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

公开(公告)号：US09489329B2

公开(公告)日：2016-11-08

申请号：US14209146

申请日：2014-03-13

Applicant: INTEL CORPORATION

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Rohit R. Verma

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/364 ,  G06F13/362 ,  G06F15/16 ,  G06F9/44

CPC classification number: G06F13/364 ,  G06F9/44 ,  G06F13/362 ,  G06F15/16

Abstract: In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定 基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。 基于此通道确定，可以将事务发送到目标代理的通道。 描述和要求保护其他实施例。

公开(公告)号：US09122815B2

公开(公告)日：2015-09-01

申请号：US14326654

申请日：2014-07-09

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Robert P. Adler ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Rohit R. Verma

IPC: G06F15/16 ,  G06F13/42 ,  G06F15/78 ,  G06F9/46

CPC classification number: G06F13/42 ,  G06F9/466 ,  G06F15/7825 ,  G06F15/7864 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于输入耦合到结构的代理的代理状态机的信用初始化状态以便初始化该结构的交易信用跟踪器中的信用的方法。 该跟踪器跟踪给定交易类型的代理的第一渠道的交易队列的信用。 然后，代理可以断言信用初始化信号，以使得信用被存储在与第一交易类型的代理的第一渠道的交易队列的数量相对应的交易信用跟踪器中。 描述和要求保护其他实施例。

公开(公告)号：US09026682B2

公开(公告)日：2015-05-05

申请号：US13713635

申请日：2012-12-13

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US09098415B2

公开(公告)日：2015-08-04

申请号：US13691016

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20150149683A9

公开(公告)日：2015-05-28

申请号：US13691016

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F13/40

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20150019788A1

公开(公告)日：2015-01-15

申请号：US14497567

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Eran Tamari ,  Mikal C. Hunsaker ,  Sridhar Lakshmanamurthy ,  Michael T. Klinglesmith ,  Blaise Fanning

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/4036

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

Abstract translation: 根据一个实施例，芯片上的系统包括每个对应于知识产权（IP）逻辑的多个代理和用于耦合代理的结构。 该结构可以包括主消息接口和边带消息接口。 该结构还包括一个或多个路由器，以经由该边带消息接口在代理之间提供带外通信。 为了实现这种通信，路由器可以执行用于边带消息的基于个人计算机（PC）的规范的排序规则的子集。 描述和要求保护其他实施例。

公开(公告)号：US09442855B2

公开(公告)日：2016-09-13

申请号：US14583601

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US09213666B2

公开(公告)日：2015-12-15

申请号：US14497567

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Eran Tamari ,  Mikal C. Hunsaker ,  Sridhar Lakshmanamurthy ,  Michael T. Klinglesmith ,  Blaise Fanning

IPC: G06F13/14 ,  G06F13/42 ,  G06F13/366 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/4036

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

公开(公告)号：US09075929B2

公开(公告)日：2015-07-07

申请号：US14578720

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/42 ,  G06F13/368

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.