公开(公告)号：US11315798B2

公开(公告)日：2022-04-26

申请号：US16075555

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Marie Krysak ,  James M. Blackwell ,  Florian Gstrein ,  Kent N. Frasure

IPC: G03F7/039 ,  H01L21/311 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US11217456B2

公开(公告)日：2022-01-04

申请号：US16955012

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Scott B. Clendenning ,  Cen Tan ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication, and the resulting devices, are described. In an example, method of dry etching a film includes forming a transition metal oxide film having a latent pore-forming material therein. The method also includes removing a surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also includes removing the porous region of the transition metal oxide film.

公开(公告)号：US11011481B2

公开(公告)日：2021-05-18

申请号：US16461546

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  James M. Blackwell

IPC: H01L23/64 ,  H01C10/16 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/525 ,  H01L27/06 ,  H01L49/02 ,  H03K19/08

Abstract: In an example, there is disclosed a configurable impedance element, having: a first impedance network including a plurality of series impedance elements and providing an initial impedance; a trim impedance network parallel to the first impedance network, including a plurality of corresponding impedance elements to the impedance elements of the first impedance network; and antifuses between the impedance elements of the first impedance network and their corresponding impedance elements of the trim network. There is also disclosed an integrated circuit including the impedance element, and a method of manufacturing and configuring the impedance element.

公开(公告)号：US20200098629A1

公开(公告)日：2020-03-26

申请号：US16465526

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC: H01L21/768

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US10366950B2

公开(公告)日：2019-07-30

申请号：US15575808

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Robert Lindsey Bristol ,  James M. Blackwell ,  Rami Hourani

IPC: H01L23/52 ,  H01L21/31 ,  H01L21/76 ,  H01L23/532 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768

Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.

公开(公告)号：US11953826B2

公开(公告)日：2024-04-09

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

CPC classification number: G03F7/0035 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/027 ,  H01L21/0274 ,  H01L21/768 ,  H01L21/76802

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20220139823A1

公开(公告)日：2022-05-05

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20220139772A1

公开(公告)日：2022-05-05

申请号：US17087523

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Christoper Jezewski ,  Jiun-Ruey Chen ,  Miriam Reshotko ,  James M. Blackwell ,  Matthew Metz ,  Che-Yun Lin

IPC: H01L21/768 ,  H01L27/06

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material.

公开(公告)号：US11251072B2

公开(公告)日：2022-02-15

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L. Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11137681B2

公开(公告)日：2021-10-05

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.