公开(公告)号：US10998405B2

公开(公告)日：2021-05-04

申请号：US15777650

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Paul A. Zimmerman ,  Ian A. Young ,  Wilman Tsai

IPC: H01L51/05 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  C01B32/182 ,  H01L29/739 ,  H01L23/532

Abstract: Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

公开(公告)号：US20160163596A1

公开(公告)日：2016-06-09

申请号：US15044976

申请日：2016-02-16

Applicant: INTEL CORPORATION

Inventor： Paul A. Zimmerman ,  Scott B. Clendenning ,  Patricio E. Romero ,  Paul B. Fischer ,  Robert Edgeworth

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

Abstract translation: 公开了形成实现负热膨胀（NTE）材料如钨酸锆（ZrW2O8）或钨酸铪（HfW2O8）的穿硅通孔（TSV）的技术。 在一些情况下，NTE材料设置在TSV的衬底和导电芯材之间，并且用于至少部分地抵消其间的热膨胀系数（CTE）失配，从而减少热诱导的应力和/或 突出（泵送）导电芯材料。 NTE材料还可以防止导电芯材料的泄漏，电压击穿和/或扩散。 此外，NTE材料可以降低高纵横比TSV中的径向应力。 在一些情况下，本文公开的技术可以提高三维集成电路和/或其他三维封装中的TSV可靠性，增强三维集成和/或增强性能。 根据本公开，可以使用本文描述的技术的其它实施例将是显而易见的。

公开(公告)号：US09786559B2

公开(公告)日：2017-10-10

申请号：US15044976

申请日：2016-02-16

Applicant: INTEL CORPORATION

Inventor： Paul A. Zimmerman ,  Scott B. Clendenning ,  Patricio E. Romero ,  Paul B. Fischer ,  Robert Edgeworth

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/64 ,  H01L23/48 ,  H01L25/065 ,  H01L21/02 ,  H01L23/60

CPC classification number: H01L21/76898 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

公开(公告)号：US09932671B2

公开(公告)日：2018-04-03

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Patricio E. Romero ,  Scott B. Clendenning ,  Grant M. Kloster ,  Florian Gstrein ,  Harsono S. Simka ,  Paul A. Zimmerman ,  Robert L. Bristol

IPC: H01L21/336 ,  C23C16/455 ,  C23C16/18 ,  C23C16/48 ,  H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L21/033

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.