Printed wiring board and method for manufacturing the same

    公开(公告)号:US12010794B2

    公开(公告)日:2024-06-11

    申请号:US17709492

    申请日:2022-03-31

    申请人: IBIDEN CO., LTD.

    发明人: Satoru Kawai

    IPC分类号: H05K1/11 H05K3/40

    摘要: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.

    PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME 有权
    印刷电路板及其制造方法

    公开(公告)号:US20140069705A1

    公开(公告)日:2014-03-13

    申请号:US13997464

    申请日:2011-12-23

    摘要: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a first part, a second part below the first part, a third part between the first and second parts, and at least one barrier layer including a metal different from a metal of the first to third parts. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

    摘要翻译: 公开了一种印刷电路板及其制造方法。 印刷电路板包括芯绝缘层,至少一个通过芯绝缘层形成的通孔,埋在芯绝缘层中的内电路层,以及在芯绝缘层的顶表面或底表面上的外电路层 ,其中所述通孔包括第一部分,在所述第一部分下方的第二部分,所述第一部分和所述第二部分之间的第三部分以及包含不同于所述第一至第三部分的金属的金属的至少一个阻挡层。 同时形成内部电路层和通孔,从而减少工艺步骤。 由于设置了奇数电路层,所以印刷电路板具有轻薄的结构。

    FABRICATING METHOD OF CIRCUIT BOARD AND CIRCUIT BOARD
    8.
    发明申请
    FABRICATING METHOD OF CIRCUIT BOARD AND CIRCUIT BOARD 有权
    电路板和电路板的制造方法

    公开(公告)号:US20130213692A1

    公开(公告)日:2013-08-22

    申请号:US13544994

    申请日:2012-07-10

    申请人: Chen-Yueh Kung

    发明人: Chen-Yueh Kung

    IPC分类号: H05K3/00 H05K1/03

    摘要: A method of fabricating a circuit board includes the following steps. A first and a second patterned conductive layer are plated on the first and the second surface of a core substrate, respectively. A first and a second extending pad are individually plated on a first and a second pad of the first and the second patterned conductive layer, respectively. A first and a second thermal-curing type dielectric layer are individually formed on the first and the second surface to cover the first and the second patterned conductive layer and the first and the second extending pad, respectively. A portion of the first and the second thermal-curing type dielectric layer respectively covering the top of the first and the second extending pad are removed. A protective film covers the second extending pad. The extending pad is removed by an etching process.

    摘要翻译: 制造电路板的方法包括以下步骤。 第一和第二图案化导电层分别电镀在芯基板的第一和第二表面上。 第一和第二延伸焊盘分别电镀在第一和第二图案化导电层的第一和第二焊盘上。 第一和第二热固化型电介质层分别形成在第一和第二表面上以分别覆盖第一和第二图案化导电层以及第一和第二延伸焊盘。 分别覆盖第一和第二延伸垫的顶部的第一和第二热固化型电介质层的一部分被去除。 保护膜覆盖第二延伸垫。 通过蚀刻工艺去除延伸垫。

    UNDERBUMP METALLURGY EMPLOYING AN ELECTROLYTIC Cu / ELECTORLYTIC Ni / ELECTROLYTIC Cu STACK
    10.
    发明申请
    UNDERBUMP METALLURGY EMPLOYING AN ELECTROLYTIC Cu / ELECTORLYTIC Ni / ELECTROLYTIC Cu STACK 有权
    使用电解铜/电解质镍/电解铜堆栈的金属冶金

    公开(公告)号:US20120198692A1

    公开(公告)日:2012-08-09

    申请号:US13453074

    申请日:2012-04-23

    IPC分类号: H05K3/00

    摘要: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

    摘要翻译: 在包含芯,至少一个前金属互连层和至少一个背侧金属互连层的封装基板的每一侧上形成化学镀铜层。 在两个无电镀铜层上涂布光致抗蚀剂,并用光刻图案化。 第一电解Cu部分形成在无电解Cu层的暴露表面上,随后形成电解Ni部分和第二电解Cu部分。 电解Ni部分提供增强的电迁移阻力,而第二电解Cu部分提供用于焊接掩模的粘附层并且用作氧化保护层。 一些第一电解铜可以被光刻装置掩盖,以根据需要阻挡电解Ni部分和第二电解Cu部分的形成。 任选地,电解Ni部分可以直接形成在无电镀Cu层上。