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    SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER INTERFACE
    4.
    发明申请
    SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER INTERFACE 审中-公开

    公开(公告)号：US20180095674A1

    公开(公告)日：2018-04-05

    申请号：US15283124

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： Alaa R. ALAMELDEEN ,  Glenn J. HINTON ,  Blaise FANNING ,  Robert J. ROYER, JR. ,  James J. GREENSKY

    IPC: G06F3/06

    CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

    Abstract: In one embodiment, an inter-memory transfer interface having selective data compression/decompression in accordance with the present description, selects from multiple candidate processes, a compression/decompression process to compress a region of data from a near memory before transmitting the compressed data to the far memory. In another aspect, the inter-memory transfer interface stores metadata indicating the particular compression/decompression process selected to compress that region of data. The stored metadata may then be used to identify the compression/decompression technique selected to compress a particular region of data, for purposes of locating the compressed data and subsequently decompressing data of that region when read from the far memory. Other aspects are described herein.

    APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
    5.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY 审中-公开

    公开(公告)号：US20200226066A1

    公开(公告)日：2020-07-16

    申请号：US16833337

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

    IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

    NVDIMM EMULATION USING A HOST MEMORY BUFFER
    9.
    发明申请
    NVDIMM EMULATION USING A HOST MEMORY BUFFER 审中-公开

    公开(公告)号：US20190042414A1

    公开(公告)日：2019-02-07

    申请号：US15976795

    申请日：2018-05-10

    Applicant: Intel Corporation

    Inventor： Dale J. JUENEMANN ,  James A. BOYD ,  Robert J. ROYER, JR.

    IPC: G06F12/0804 ,  G06F3/06

    Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

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