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公开(公告)号:US09849363B1
公开(公告)日:2017-12-26
申请号:US15192181
申请日:2016-06-24
Applicant: Intel Corporation
Inventor: Tawfik M. Rahal-Arabi , Hong W. Wong
CPC classification number: A63B69/187 , A63B2220/05 , A63B2220/20 , A63B2244/19 , A63C19/062 , A63C2203/18 , G08B5/36
Abstract: Systems and methods for providing a slalom racing gate monitor system are provided herein. A system includes a microcontroller; a first, second, and third sensor, each coupled to the microcontroller, the first, second, and third sensors each having a field of view and disposed on a slalom pole, and disposed where the fields of view of the first, second, and third sensors substantially cover a 360 degree field of view around the slalom pole; wherein the microcontroller is to: obtain a sequence of sensor readings from a plurality of sensors of the first, second, and third sensors, each reading in the sequence of sensor readings indicating an object detected in the field of view of the respective sensor; determine whether the object passed the slalom pole on a correct side; and present a notification of whether the object passed the slalom pole on the correct side.
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公开(公告)号:US11188132B2
公开(公告)日:2021-11-30
申请号:US15169350
申请日:2016-05-31
Applicant: INTEL CORPORATION
Inventor: Yu Liang Shiao , Tawfik M. Rahal-Arabi , Chang-Wu Yen , Celia H. Yang
Abstract: Modular power delivery techniques for electronic devices are described. In one embodiment, an apparatus may comprise native power delivery circuitry to source a native power delivery current, power management circuitry to control the native power delivery circuitry, a power delivery connector to mate with a counterpart power delivery connector of an external device, and a processing device conductively coupled to the power delivery connector via a supplemental power delivery line, the processing device to draw a supplemental power delivery current from the external device via the supplemental power delivery line. Other embodiments are described and claimed.
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公开(公告)号:US20170368437A1
公开(公告)日:2017-12-28
申请号:US15192181
申请日:2016-06-24
Applicant: Intel Corporation
Inventor: Tawfik M. Rahal-Arabi , Hong W. Wong
CPC classification number: A63B69/187 , A63B2220/05 , A63B2220/20 , A63B2244/19 , A63C19/062 , A63C2203/18 , G08B5/36
Abstract: Systems and methods for providing a slalom racing gate monitor system are provided herein. A system includes a microcontroller; a first, second, and third sensor, each coupled to the microcontroller, the first, second, and third sensors each having a field of view and disposed on a slalom pole, and disposed where the fields of view of the first, second, and third sensors substantially cover a 360 degree field of view around the slalom pole; wherein the microcontroller is to: obtain a sequence of sensor readings from a plurality of sensors of the first, second, and third sensors, each reading in the sequence of sensor readings indicating an object detected in the field of view of the respective sensor; determine whether the object passed the slalom pole on a correct side; and present a notification of whether the object passed the slalom pole on the correct side.
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公开(公告)号:US09710030B2
公开(公告)日:2017-07-18
申请号:US14570945
申请日:2014-12-15
Applicant: Intel Corporation
Inventor: Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric Distefano , James G. Hermerding, II
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3203 , Y02D10/16
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
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公开(公告)号:US09898067B2
公开(公告)日:2018-02-20
申请号:US15089350
申请日:2016-04-01
Applicant: Intel Corporation
Inventor: Eric Distefano , Guy M. Therien , Vasudevan Srinivasan , Tawfik M. Rahal-Arabi , Venkatesh Ramani , Ryan D. Wells , Stephen H. Gunther , Jeremy J. Shrall , James G. Hermerding, II
CPC classification number: G06F1/3234 , G06F1/206 , G06F1/26 , Y02D10/16
Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.
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公开(公告)号:US09189056B2
公开(公告)日:2015-11-17
申请号:US13727113
申请日:2012-12-26
Applicant: Intel Corporation
Inventor: Tawfik M. Rahal-Arabi , Alexander B. Uan-Zo-Li , Mark MacDonald , Vivek M. Paranjape , Andy Keates , Don J. Nguyen
CPC classification number: G06F1/3203 , G06F1/263 , G06F1/28 , G06F1/3206 , G06F1/3212 , G06F1/3234 , G06F1/324 , G06F1/3296 , H01M10/4207 , H01M10/4257 , H01M10/482 , H01M10/486 , H01M16/00 , H01M2010/4271 , H02J9/04 , H04W52/0261 , Y02D10/126 , Y02D10/172 , Y02D10/174 , Y02D70/00 , Y02D70/1224 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y10T307/625
Abstract: Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein.
Abstract translation: 各种实施例通常涉及由第一和第二组能量存储单元供电的计算设备的操作,第一组的单元在结构上优化用于更高密度的电力存储,并且第二组的单元在结构上被优化用于提供电 功率在高电流水平。 电池模块包括壳体,设置在壳体内以存储高密度的电能的第一单元和设置在壳体内的第二单元,以提供其中存储有高电流水平的电能。 在此描述和要求保护的其它实施例。
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公开(公告)号:US11301011B2
公开(公告)日:2022-04-12
申请号:US16696072
申请日:2019-11-26
Applicant: INTEL CORPORATION
Inventor: Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric DiStefano , James G. Hermerding, II
IPC: G06F1/26 , G06F1/32 , G06F1/20 , G06F1/3203
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
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公开(公告)号:US20200218319A1
公开(公告)日:2020-07-09
申请号:US16696072
申请日:2019-11-26
Applicant: INTEL CORPORATION
Inventor: Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric DiStefano , James G. Hermerding, II
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
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9.
公开(公告)号:US20150100799A1
公开(公告)日:2015-04-09
申请号:US14570945
申请日:2014-12-15
Applicant: Intel Corporation
Inventor: Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric Distefano , James G. Hermerding, II
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3203 , Y02D10/16
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
Abstract translation: 描述了可配置的处理器热管理的装置,系统和方法的实施例。 例如,设备可以包括处理器,其被布置成以包括热限制模式,正常热限制模式和热限制模式的多个热模式操作,以及热管理逻辑,其可操作以基于 设备的一个或多个属性。 描述和要求保护其他实施例。
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公开(公告)号:US10133331B2
公开(公告)日:2018-11-20
申请号:US14920449
申请日:2015-10-22
Applicant: Intel Corporation
Inventor: Tawfik M. Rahal-Arabi , Alexander B. Uan-Zo-Li , Mark MacDonald , Vivek M. Paranjape , Andy Keates , Don J. Nguyen
Abstract: Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein.
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