公开(公告)号：US11562959B2

公开(公告)日：2023-01-24

申请号：US16912638

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Teong Guan Yew ,  Choong Kooi Chee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.

公开(公告)号：US20160285757A1

公开(公告)日：2016-09-29

申请号：US14670213

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Teong Guan Yew

IPC: H04L12/721 ,  H04L12/10

CPC classification number: H04L45/566 ,  H04L12/10 ,  H04L49/109

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

Abstract translation: 第一集成电路的端口耦合到第一通信路径。 配置信息通过端口和第一通信路径在连接到第二设备的连接器和第二集成电路之间传送。 该端口与第一通信路径分离。 端口耦合到第二通信路径。 数据通过端口和第二通信路径在连接器和第二集成电路之间传送。

公开(公告)号：US11805602B2

公开(公告)日：2023-10-31

申请号：US17089736

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee ,  Teong Guan Yew

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K3/34 ,  H05K3/32

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H05K3/323 ,  H05K3/3436 ,  H01L2224/16225 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10992

Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

公开(公告)号：US11527481B2

公开(公告)日：2022-12-13

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi Chee ,  Bok Eng Cheah ,  Teong Guan Yew ,  Jackson Chung Peng Kong ,  Loke Yip Foo

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US10084698B2

公开(公告)日：2018-09-25

申请号：US14670213

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Teong Guan Yew

IPC: H04L12/721 ,  H04L12/10 ,  H04L12/933

CPC classification number: H04L45/566 ,  H04L12/10 ,  H04L49/109

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

公开(公告)号：US10014710B2

公开(公告)日：2018-07-03

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Mark A. Schaecher ,  Teong Guan Yew ,  Eng Huat Goh

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/18 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.