公开(公告)号：US08945952B2

公开(公告)日：2015-02-03

申请号：US14071894

申请日：2013-11-05

Applicant: Intermolecular Inc.

Inventor： John Foster

IPC: H01L21/66 ,  H01L21/302 ,  H01L21/461 ,  C23F1/00 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/8238

CPC classification number: H01L21/30604 ,  H01L21/02071 ,  H01L21/32134 ,  H01L21/67086 ,  H01L21/823828 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract translation: 提供了组合工作流程，用于在形成晶体管器件的栅极结构之后评估清洁过程，为栅极堆叠形成提供优化的工艺条件，包括使用高k电介质的金属栅极堆叠。 NMOS和PMOS晶体管器件组合地制造在衬底的多个区域上，每个区域暴露于不同的清洁化学和工艺。 然后对晶体管器件进行表征，并对数据进行比较，对不同清洁化学品和工艺的潜在损害进行分类。 可以获得优化的化学品和工艺以满足所需的装置要求。

公开(公告)号：US20150371872A1

公开(公告)日：2015-12-24

申请号：US14313120

申请日：2014-06-24

Applicant: Intermolecular Inc.

Inventor： John Foster ,  Sean Lin ,  Muthumanickam Sankarapandian ,  Ruilong Xie

IPC: H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32134 ,  H01L21/28088 ,  H01L21/67086 ,  H01L29/66545

Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C. The titanium carbide structures may be etched in a solution that also includes ammonium hydroxide, in addition to hydrogen peroxide, and maintained at about 25° C.

Abstract translation: 提供了使用门最后方法制造晶体管的方法。 这些方法包括蚀刻氮化钛和碳化钛结构，同时保留高k电介质结构。 碳化钛结构还可以包括铝。 蚀刻可以在一种或多种蚀刻溶液中进行，每种蚀刻溶液包括过氧化氢。 氮化钛和碳化钛结构可以在相同的蚀刻溶液中同时（非选择性地）蚀刻，除了过氧化氢之外还包括盐酸，并保持在约25℃和85℃。在一些实施方案中，钛 氮化物结构和碳化钛结构可以在不同的操作中分别（选择性地）蚀刻并使用不同的蚀刻溶液。 可以在保持在约25℃和85℃的稀释过氧化氢溶液中蚀刻氮化钛结构。可以在除了过氧化氢之外也包括氢氧化铵的溶液中蚀刻碳化钛结构，并保持在 约25°C

公开(公告)号：US20150132953A1

公开(公告)日：2015-05-14

申请号：US14079473

申请日：2013-11-13

Applicant: Intermolecular Inc.

Inventor： Gregory Nowling ,  John Foster

IPC: H01L21/3213

CPC classification number: H01L21/32133 ,  C23F1/26 ,  C23F4/00 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/67086 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

Abstract translation: 两步工艺顺序均匀地蚀刻基材上的钨基和钛基结构。 使用过氧化物和加热的硝酸的湿蚀刻序列均匀地凹陷包括W，TiN和TiAl的金属堆叠。 W，TiN和TiC在〜25℃下通过过氧化物蚀刻均匀地凹陷，随后在〜60℃下加入非常少量的加成过氧化物的酸溶液。在没有刻蚀沟槽氧化物或其他金属的功函数金属中蚀刻TiC （1）在25-35℃高浓度超稀释HF，（2）在25-60℃稀释HCl，（3）在25-60℃稀释NH 4 OH，或（4）溶液（2） 或（3）少量过氧化物。 然后，堆叠中的其它金属可以被等离子体蚀刻而不被TiC残留物阻挡。

公开(公告)号：US20140179082A1

公开(公告)日：2014-06-26

申请号：US13725358

申请日：2012-12-21

Applicant: INTERMOLECULAR INC.

Inventor： John Foster ,  Kim Van Berkel

IPC: H01L21/306 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31111 ,  H01L21/67086 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

Abstract: Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as one or more of silicon nitride, silicon oxide, polysilicon, and titanium nitride structures. Selected etching solution compositions and processing conditions provide high etching selectivity of hafnium oxide relative to these other materials. As such, hafnium oxide structures may be partially or completely removed without significant damage to other exposed structures made from these other materials. In some embodiments, the etching rate hafnium oxide is two or more times greater than the etching rate of silicon oxide and/or twenty or more times greater that the etching rate of polysilicon. The etching rate of hafnium oxide may be one and half times greater than the etching rate of silicon nitride and/or five or more times greater than the etching rate of titanium nitride.

Abstract translation: 提供了用于处理具有氧化铪结构的半导体衬底以及氮化硅，氧化硅，多晶硅和氮化钛结构中的一种或多种的方法。 所选择的蚀刻溶液组合物和加工条件相对于这些其它材料提供氧化铪的高蚀刻选择性。 因此，氧化铪结构可以部分或完全去除，而不会对由这些其它材料制成的其它暴露结构造成显着的损害。 在一些实施例中，蚀刻速率铪氧化物比氧化硅的蚀刻速率大两倍或更多倍，和/或多晶硅的蚀刻速率的二十或更多倍。 氧化铪的蚀刻速率可以比氮化硅的蚀刻速度大一倍以上，或比氮化钛的蚀刻速度大五倍以上。

公开(公告)号：US20130285159A1

公开(公告)日：2013-10-31

申请号：US13656220

申请日：2012-10-19

Applicant: Intermolecular Inc.

Inventor： John Foster ,  Kim Van Berkel

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66477

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.

Abstract translation: 提供了蚀刻金属栅极叠层的方法。 该方法包括在衬底上形成栅极堆叠，其中栅极堆叠包括金属栅极。 在栅极堆叠上执行湿蚀刻工艺。 湿蚀刻工艺包括将具有栅极堆叠的衬底浸入由湿蚀刻剂和氧化剂组成的水溶液中，从溶液中除去衬底并从蚀刻的栅极堆叠中冲洗溶液。

公开(公告)号：US09330937B2

公开(公告)日：2016-05-03

申请号：US14079473

申请日：2013-11-13

Applicant: Intermolecular Inc.

Inventor： Gregory Nowling ,  John Foster

IPC: C23F1/00 ,  C03C15/00 ,  C03C25/68 ,  C25F3/00 ,  H01L21/3213 ,  H01L21/67 ,  H01J37/32 ,  C23F1/26 ,  C23F4/00

CPC classification number: H01L21/32133 ,  C23F1/26 ,  C23F4/00 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/67086 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

公开(公告)号：US20140179112A1

公开(公告)日：2014-06-26

申请号：US13726760

申请日：2012-12-26

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES

Inventor： John Foster ,  Sven Metzger

IPC: H01L21/306

CPC classification number: H01L21/32134 ,  H01L21/28088 ,  H01L21/28123 ,  H01L22/30 ,  H01L29/517 ,  H01L29/6653

Abstract: Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7% by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40° C. and 60° C.

Abstract translation: 提供了半导体基板的高效率组合测试方法，每个包括多个位置隔离区域。 每个位置分离区域包括氮化钛结构以及氧化铪结构和/或多晶硅结构。 每个位置分离区域暴露于包括硫酸，过氧化氢和氟化氢的蚀刻溶液。 蚀刻溶液的组成和/或蚀刻条件在位置分离区域之间变化，以研究该变化对氮化钛相对于氧化铪和/或多晶硅的蚀刻选择性的影响以及蚀刻速率。 蚀刻溶液中硫酸和/或过氧化氢的浓度可以小于7体积％，而氟化氢的浓度可以在50ppm和200ppm之间。 在一些实施例中，蚀刻溶液的温度保持在约40℃至60℃之间。

公开(公告)号：US08575016B1

公开(公告)日：2013-11-05

申请号：US13656220

申请日：2012-10-19

Applicant: Intermolecular Inc.

Inventor： John Foster ,  Kim Van Berkel

IPC: H01L21/3205

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66477

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.

Abstract translation: 提供了蚀刻金属栅极叠层的方法。 该方法包括在衬底上形成栅极堆叠，其中栅极堆叠包括金属栅极。 在栅极堆叠上执行湿蚀刻工艺。 湿蚀刻工艺包括将具有栅极堆叠的衬底浸入由湿蚀刻剂和氧化剂组成的水溶液中，从溶液中除去衬底并从蚀刻的栅极堆叠中冲洗溶液。

公开(公告)号：US09831100B2

公开(公告)日：2017-11-28

申请号：US14313120

申请日：2014-06-24

Applicant: Intermolecular Inc. ,  International Business Machines

Inventor： John Foster ,  Sean Lin ,  Muthumanickam Sankarapandian ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/32134 ,  H01L21/28088 ,  H01L21/67086 ,  H01L29/66545

Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C. The titanium carbide structures may be etched in a solution that also includes ammonium hydroxide, in addition to hydrogen peroxide, and maintained at about 25° C.

公开(公告)号：US20160181087A1

公开(公告)日：2016-06-23

申请号：US14576554

申请日：2014-12-19

Applicant: Intermolecular Inc. ,  IBM-International Business Machines Corporation

Inventor： John Foster ,  Steven Bentley ,  Sean Lin ,  Dave Rath ,  Muthumanickam Sankarapandian ,  Ruilong Xie

IPC: H01L21/02 ,  B08B3/10 ,  B08B3/08

CPC classification number: H01L21/02068 ,  C11D11/0047 ,  H01L21/02052

Abstract: Particle-clean formulations and methods for semiconductor substrates use aqueous solutions of tetraethylammonium hydroxide (“TEAH,” C8H21NO) with or without hydrogen peroxide (H2O2). The solution pH ranges from 8-12.5. At process temperatures between 20-70 C, the TEAH solutions have been observed to remove particles from silicon-germanium (SiGe) with 20-99% Ge content in 15-300 seconds with very little etching (SiGe etch rates

Abstract translation: 用于半导体衬底的颗粒清洁配方和方法使用具有或不具有过氧化氢（H 2 O 2）的四乙基氢氧化铵（“TEAH”，C 8 H 21 NO）的水溶液。 溶液pH范围为8-12.5。 在20-70℃的工艺温度下，已经观察到TEAH溶液在15-300秒内以非常少的蚀刻（SiGe蚀刻速率<1nm / min）从15-00秒钟内以20-99％Ge含量的硅 - 锗（SiGe）去除颗粒 ）。