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    Semiconductor-on-insulator (SOI) deep trench capacitor
    3.
    发明授权
    Semiconductor-on-insulator (SOI) deep trench capacitor 有权
    绝缘体上半导体（SOI）深沟槽电容器

    公开(公告)号：US09059322B2

    公开(公告)日：2015-06-16

    申请号：US13625286

    申请日：2012-09-24

    Applicant: International Business Machines Corporation

    Inventor： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC: H01L27/108 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L49/02

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/91 ,  H01L29/945

    Abstract: Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening.

    Abstract translation: 本发明的方面涉及绝缘体上半导体（SOI）深沟槽电容器。 一个实施例包括形成深沟槽电容器结构的方法。 该方法包括：提供在SOI结构的半导体层中包括第一和第二沟槽开口的SOI结构，形成覆盖半导体层的掺杂半导体层，形成覆盖掺杂半导体层的第一介电层，形成节点金属层 在所述第一电介质层上形成覆盖所述节点金属层的第二电介质层，用金属层填充每个沟槽开口的剩余部分，以在每个所述沟槽开口中形成内部节点，所述金属层包括： 并且形成节点连接结构，以将第一沟槽开口中的节点金属层与第二沟槽开口中的节点金属层导电连接。

    SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
    4.
    发明申请
    SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 审中-公开
    具有深度电容电容器的半导体结构及其制造方法

    公开(公告)号：US20150135156A1

    公开(公告)日：2015-05-14

    申请号：US14601288

    申请日：2015-01-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

    IPC: G06F17/50

    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

    Abstract translation: 公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。 该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。 该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。 该方法还包括在多晶硅鳍片上形成绝缘体层。 该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。

    Uniform finFET gate height
    6.
    发明授权
    Uniform finFET gate height 有权
    均匀finFET栅极高度

    公开(公告)号：US08928057B2

    公开(公告)日：2015-01-06

    申请号：US13689924

    申请日：2012-11-30

    Applicant: International Business Machines Corporation

    Inventor： William Cote ,  Johnathan E. Faltermeier ,  Babar A. Khan ,  Ravikumar Ramachandran ,  Theodorus E. Standaert ,  Xinhui Wang

    IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L29/945 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66181 ,  H01L29/66545

    Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

    Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的散热片，所述氧化物层位于所述散热片和所述氮化物层之间，去除所述翅片的一部分以形成开口，形成介电隔离物 开口的侧壁，并用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平。 该方法还可以包括形成与其中一个鳍片成直角的深沟槽电容器，去除氮化物层以在散热片和填充材料之间形成间隙，其中填充材料具有在间隙上延伸的重新排列的几何形状，以及 去除重入的几何形状并使翅片和填充材料之间的间隙变宽。

    DRAM WITH DUAL LEVEL WORD LINES
    7.
    发明申请
    DRAM WITH DUAL LEVEL WORD LINES 有权
    DRAM与双级字线

    公开(公告)号：US20140065777A1

    公开(公告)日：2014-03-06

    申请号：US14077351

    申请日：2013-11-12

    Applicant: International Business Machines Corporation

    Inventor： Babar A. Khan ,  Effendi Leobandung

    IPC: H01L27/108 ,  H01L27/12

    CPC classification number: H01L27/10867 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/945

    Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

    Abstract translation: 深沟槽电容器上的顶部半导体层和导电帽结构通过蚀刻同时构图。 导电盖结构的每个图案化部分构成导电盖结构，其横向接触作为顶部半导体层的图案化剩余部分之一的半导体材料部分。 栅电极形成为不互连的离散结构。 在接触电介质层的形成和平坦化之后，通过栅极线形成在接触电介质层上方的线路电平以提供与栅电极的电连接。 彼此电连接的栅极电极和通过栅极线构成跨越两个电平存在的栅极线。

    CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
    8.
    发明申请
    CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE 有权
    在基础上创建深度倾斜

    公开(公告)号：US20140021585A1

    公开(公告)日：2014-01-23

    申请号：US14036474

    申请日：2013-09-25

    Applicant: International Business Machines Corporation

    Inventor： Jennifer E. Appleyard ,  John E. Barth ,  John B. DeForge ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson ,  Andrew A. Turner

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L27/0805 ,  H01L28/91 ,  H01L29/945

    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

    Abstract translation: 公开了半导体结构及其制造方法。 在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。 每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。 第一氧化物层设置在第一衬底上。 可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

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