公开(公告)号：US20150106780A1

公开(公告)日：2015-04-16

申请号：US14551693

申请日：2014-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeanne P. BICKFORD ,  Nazmul HABIB ,  Baozhen LI ,  Pascal A. NSAME

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F2217/10

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract translation: 半导体器件设计期间半导体器件可靠性鉴定的系统和方法。 提供了一种方法，其中包括为性能窗口定义性能过程窗口。 该方法还包括确定每个仓分配的至少一个故障机制。 所述方法还包括当所述至少一个故障机制是所述过程窗口的函数时产生不同的可靠性模型，以及当所述至少一个故障机制不是所述过程窗口的功能时，生成公共可靠性模型。 该方法还包括识别用于每个仓分配的至少一个风险因素，以及使用生产线分布生成聚合模型。 该方法还包括通过bin确定故障率并优化线路中心以最小化产品故障率。 该方法还包括根据制造线偏移事件来确定废料箱的故障率和报废产量。

公开(公告)号：US20140380261A1

公开(公告)日：2014-12-25

申请号：US13922311

申请日：2013-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeanne P. BICKFORD ,  Nazmul HABIB ,  Baozhen LI ,  Pascal A. NSAME

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F2217/10

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract translation: 半导体器件设计期间半导体器件可靠性鉴定的系统和方法。 提供了一种方法，其中包括为性能窗口定义性能过程窗口。 该方法还包括确定每个仓分配的至少一个故障机制。 所述方法还包括当所述至少一个故障机制是所述过程窗口的函数时产生不同的可靠性模型，以及当所述至少一个故障机制不是所述过程窗口的功能时，生成公共可靠性模型。 该方法还包括识别用于每个仓分配的至少一个风险因素，以及使用生产线分布生成聚合模型。 该方法还包括通过bin确定故障率并优化线路中心以最小化产品故障率。 该方法还包括根据制造线偏移事件来确定废料箱的故障率和报废产量。

公开(公告)号：US20190363013A1

公开(公告)日：2019-11-28

申请号：US16288803

申请日：2019-02-28

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Baozhen LI ,  Kirk David PETERSON ,  John E. SHEETS, II ,  Junli WANG ,  Chih-Chao YANG

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/285

Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.

公开(公告)号：US20160379927A1

公开(公告)日：2016-12-29

申请号：US15260675

申请日：2016-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. CLEVENGER ,  Baozhen LI ,  Kirk D. PETERSON

IPC: H01L23/528 ,  H01L23/532 ,  G06F17/50 ,  H01L21/321 ,  H01L21/311 ,  H01L21/285 ,  H01L21/288 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/82 ,  H01L21/0217 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.

公开(公告)号：US20230197606A1

公开(公告)日：2023-06-22

申请号：US17645208

申请日：2021-12-20

Applicant: International Business Machines Corporation

Inventor： Baozhen LI ,  Chih-Chao YANG ,  Ashim DUTTA ,  Huimei ZHOU

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283

Abstract: Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

公开(公告)号：US20180096890A1

公开(公告)日：2018-04-05

申请号：US15285212

申请日：2016-10-04

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Baozhen LI ,  Kirk David Peterson ,  John E. SHEETS, II ,  Junli WANG ,  Chih-Chao YANG

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.

公开(公告)号：US20160379877A1

公开(公告)日：2016-12-29

申请号：US15260679

申请日：2016-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. CLEVENGER ,  Baozhen LI ,  Kirk D. PETERSON

IPC: H01L21/768 ,  H01L21/66 ,  G06F17/50 ,  H01L23/532

CPC classification number: H01L23/528 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/82 ,  H01L21/0217 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.

公开(公告)号：US20160163651A1

公开(公告)日：2016-06-09

申请号：US14561514

申请日：2014-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. CLEVENGER ,  Baozhen LI ,  Kirk D. PETERSON

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/321 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L23/528 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/82 ,  H01L21/0217 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.

Abstract translation: 公开了用于电阻或电迁移的优化金属线，其制造方法和设计方法。 该方法包括在开口内和电介质材料的表面上沉积金属材料，导致金属填充的开口和与金属填充的开口对准的凹陷区域的形貌。 该方法还包括在金属材料上沉积合金材料，包括在凹陷区域内。 该方法还包括使金属材料平坦化，将合金材料留在凹陷区域内。 该方法还包括将合金材料扩散到形成与金属填充开口自对准的合金化区域的金属材料中。

公开(公告)号：US20150035158A1

公开(公告)日：2015-02-05

申请号：US14515925

申请日：2014-10-16

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. GAMBINO ,  David L. HARAME ,  Baozhen LI ,  Timothy D. SULLIVAN ,  Bjorn K.A. ZETTERLUND

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.

Abstract translation: 公开了具有增强的电迁移性能和制造方法的半导体器件。 该方法包括形成与装置电接触的至少一个金属线。 该方法还包括形成与至少一个金属线电接触的至少一个钉结构。 形成至少一个钉结构，使得通过至少一个金属线的电流也穿过至少缝合结构以减少电迁移问题。