公开(公告)号：US20150228753A1

公开(公告)日：2015-08-13

申请号：US14698206

申请日：2015-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  YU LU ,  KEITH KWONG HON WONG

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/306 ,  H01L21/04 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹槽中形成源极和漏极接触。 源极和漏极触点在沟道层上方延伸。

公开(公告)号：US20180111833A1

公开(公告)日：2018-04-26

申请号：US15488751

申请日：2017-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SHU-JEN HAN ,  BHARAT KUMAR ,  GEORGE S. TULEVSKI

IPC: C01B32/174 ,  H01L21/02 ,  H01L51/00

CPC classification number: H01L51/0048 ,  C01B32/16 ,  C01B32/168 ,  C01B32/174 ,  C07F9/3808 ,  H01L21/02606 ,  H01L51/0012

Abstract: Structures and methods that include selective electrostatic placement based on a dipole-to-dipole interaction of electron-rich carbon nanotubes onto an electron-deficient pre-patterned surface. The structure includes a substrate with a first surface having a first isoelectric point and at least one additional surface having a second isoelectric point. A self-assembled monolayer is selectively formed on the first surface and includes an electron deficient compound including a deprotonated pendant hydroxamic acid or a pendant phosphonic acid group or a pendant catechol group bound to the first surface. An organic solvent can be used to deposit the electron rich carbon nanotubes on the self-assembled monolayer.

公开(公告)号：US20180102438A1

公开(公告)日：2018-04-12

申请号：US15840354

申请日：2017-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ZHIHONG CHEN ,  SHU-JEN HAN ,  SIYURANGA O. KOSWATTA ,  ALBERTO VALDES GARCIA

IPC: H01L29/93 ,  H01L29/16 ,  B82Y10/00 ,  H01L49/02 ,  B82Y40/00

CPC classification number: H01L29/93 ,  B82Y10/00 ,  B82Y40/00 ,  H01L28/40 ,  H01L29/1606

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

公开(公告)号：US20180090324A1

公开(公告)日：2018-03-29

申请号：US15588976

申请日：2017-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/2807 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32056 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

公开(公告)号：US20140151642A1

公开(公告)日：2014-06-05

申请号：US13968026

申请日：2013-08-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SHU-JEN HAN ,  ALBERTO VALDES GARCIA

IPC: H01L29/16

CPC classification number: H01L29/16 ,  B82Y30/00 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/778 ,  H01L2224/05568 ,  H01L2224/13023

Abstract: Three-dimensional integrated circuits include an active layer having one or more active components formed with carbon-based channel material; a passive layer monolithically formed with the active layer, having one or more sub-layers and each sub-layer having one or more passive components, where the passive components have monolithically formed vertical interconnects to components on other layers; and a surface layer monolithically formed with the passive layer, including one or more surface components connected to one or more of the passive components through monolithically formed vias.

Abstract translation: 三维集成电路包括具有由碳基通道材料形成的一个或多个活性组分的活性层; 一个有源层单片形成的无源层，具有一个或多个子层，每个子层具有一个或多个无源部件，其中无源部件具有与其它层上的部件一体形成的垂直互连; 以及与被动层一体形成的表层，包括通过单片形成的通孔连接到一个或多个无源部件的一个或多个表面部件。

公开(公告)号：US20190259953A1

公开(公告)日：2019-08-22

申请号：US16401433

申请日：2019-05-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ABRAM L. FALK ,  SHU-JEN HAN ,  BHARAT KUMAR

IPC: H01L51/00 ,  B32B5/06 ,  D06M11/74 ,  D06M23/08 ,  H01G11/36 ,  D06M11/83 ,  B32B5/02 ,  B32B5/26

Abstract: A textile article includes a first fabric including a plurality of first carbon nanotubes coupled to the first fabric. The first carbon nanotubes of the plurality of first carbon nanotubes are metallic carbon nanotubes. A second fabric includes a plurality of second carbon nanotubes coupled to the second fabric. The second carbon nanotubes of the plurality of second carbon nanotubes are semiconductive carbon nanotubes. The first fabric is interconnected with the second fabric.

公开(公告)号：US20180350603A1

公开(公告)日：2018-12-06

申请号：US16042405

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/2807 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32056 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

公开(公告)号：US20140312412A1

公开(公告)日：2014-10-23

申请号：US13864760

申请日：2013-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  YU LU ,  KEITH KWONG HON WONG

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹部中形成源极和漏极接触，其中源极和漏极接触在沟道层上方延伸。

公开(公告)号：US20130244386A1

公开(公告)日：2013-09-19

申请号：US13863017

申请日：2013-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  KEITH KWONG HON WONG ,  JUN YUAN

IPC: H01L29/66

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅电极，并且在掩埋栅电极之上构图包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20190385854A1

公开(公告)日：2019-12-19

申请号：US16547948

申请日：2019-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/40 ,  B82Y10/00 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  H01L29/49

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.