公开(公告)号：US20240105769A1

公开(公告)日：2024-03-28

申请号：US17935992

申请日：2022-09-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shahab Siddiqui ,  Ruqiang Bao ,  Charlotte DeWan Adams ,  Curtis S. Durfee ,  Anthony I. Chou ,  Barry Paul Linder ,  Ravikumar Ramachandran ,  Dechao Guo

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

摘要： A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

公开(公告)号：US20230411386A1

公开(公告)日：2023-12-21

申请号：US17807795

申请日：2022-06-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Albert M. Chu ,  Junli Wang ,  Brent A. Anderson ,  Anthony I. Chou ,  Dechao Guo

IPC分类号： H01L27/088 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

摘要： A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.

公开(公告)号：US20230335585A1

公开(公告)日：2023-10-19

申请号：US17722376

申请日：2022-04-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Albert M. Chu ,  Albert M. Young ,  Anthony I. Chou ,  Junli Wang ,  Brent A. Anderson

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234 ,  H01L25/07 ,  H01L23/528

CPC分类号： H01L29/0665 ,  H01L29/66545 ,  H01L29/78696 ,  H01L21/823412 ,  H01L29/66742 ,  H01L25/074 ,  H01L23/5283

摘要： A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.

公开(公告)号：US09837319B2

公开(公告)日：2017-12-05

申请号：US15076036

申请日：2016-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/40 ,  H01L21/84

CPC分类号： H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

摘要： An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20170338145A1

公开(公告)日：2017-11-23

申请号：US15669260

申请日：2017-08-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/06 ,  H01L23/522

CPC分类号： H01L21/76283 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US09703301B1

公开(公告)日：2017-07-11

申请号：US15190254

申请日：2016-06-23

申请人： International Business Machines Corporation

发明人： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC分类号： G05D23/20 ,  G05D23/24 ,  G01K7/16

CPC分类号： G05D23/24 ,  G01K7/16 ,  H01C3/04 ,  H01C17/232 ,  H01C17/267 ,  H01L22/14

摘要： Embodiments include methods, computer systems and computer program products for controlling resistance value of a resistor in a circuit. Aspects include: retrieving, via a controller, a set of parameters of the resistor from a non-volatile memory in the circuit, detecting, via the controller, an operating temperature of the resistor during circuit operation in field using a temperature sensor, generating, by the controller, a temperature difference between the operating temperature detected and a target temperature at which the resistor has a target resistance value, producing, by the controller, a control signal responsive to the temperature difference generated, and transmitting the control signal to a temperature regulator placed adjacent to the resistor to adjust the resistance value of the resistor. The resistance value of the resistor varies in response to temperature changes around the resistor according to a temperature coefficient of the resistance of the resistor.

公开(公告)号：US20160307918A1

公开(公告)日：2016-10-20

申请号：US15196681

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L27/12 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/06 ,  H01L23/525 ,  H01L29/51 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

摘要翻译： 公开了具有集成的被动结构的金属氧化物半导体场效应晶体管（MOSFET）及其制造方法。 该方法包括在有源区域中形成层叠结构，以及在层叠结构附近形成至少一个浅沟槽隔离（STI）结构。 该方法还包括形成直接与至少一个STI结构和堆叠结构接触的半导体层。 该方法还包括图案化半导体层和层叠结构，以在有源区域中形成有源器件，并且在至少一个STI结构上直接形成半导体层的无源结构。

公开(公告)号：US09190418B2

公开(公告)日：2015-11-17

申请号：US14217572

申请日：2014-03-18

申请人： International Business Machines Corporation

发明人： Anthony I. Chou ,  Murshed M. Chowdhury ,  Arvind Kumar ,  Robert R. Robison

IPC分类号： H01L21/76 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/324 ,  H01L21/225 ,  H01L21/265 ,  H01L29/167

CPC分类号： H01L27/1203 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

摘要： After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.

摘要翻译： 在绝缘体上半导体（SOI）衬底的顶部半导体层中形成源极/漏极沟槽之后，半导体结构的相邻沟道区的沟槽的部分被形成在沟槽的侧壁上的牺牲隔离物或由光刻胶层 部分。 牺牲间隔物或光致抗蚀剂层部分屏蔽沟槽下方的顶部半导体层的部分以及后续的离子注入以形成结对接。 因此，离子注入区仅限于远离半导体结构的沟道区的顶部半导体层的未屏蔽的亚层部分。 控制离子注入区域的宽度，使得注入的掺杂剂在随后的热循环期间不扩散到沟道区域中，以便抑制短沟道效应。

公开(公告)号：US09064972B2

公开(公告)日：2015-06-23

申请号：US14220437

申请日：2014-03-20

申请人： International Business Machines Corporation

发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/739 ,  H01L29/861 ,  H01L27/06 ,  H01L27/12 ,  H01L21/265 ,  H01L21/77

CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

摘要： A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

摘要翻译： 一种制造半导体结构的方法，该半导体结构设置有具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的多个门控二极管和由非硅化栅极材料制成的高K栅极堆叠 与FET相邻的二极管，其每一个具有硅化源，硅化物漏极和硅化HiK栅极堆叠。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

公开(公告)号：US20150123190A1

公开(公告)日：2015-05-07

申请号：US14591048

申请日：2015-01-07

申请人： International Business Machines Corporation

发明人： Anthony I. Chou ,  Arvind Kumar

IPC分类号： H01L27/12 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/1203 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/7883

摘要： A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.

摘要翻译： 提供用于集成SOI CMOS FET和NVRAM存储器件的结构和方法。 该结构包括含有半导体衬底，SOI层和形成在半导体衬底和SOI层之间的BOX层的SOI衬底。 SOI衬底包括预定义的SOI器件和NVRAM器件区域。 在SOI器件区域中形成SOI FET。 SOI FET包括BOX层和SOI层的部分，SOI FET栅极电介质层和栅极导体层。 该结构还包括形成在NVRAM器件区域中的NVRAM器件。 NVRAM器件包括隧道氧化物，浮动栅极，阻塞氧化物和控制栅极层。 隧道氧化物层与SOI器件区域中BOX层的部分共面。 浮置栅极层与SOI器件区域中的半导体层的部分共面。