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    Embedded harmonic termination on high power RF transistor
    1.
    发明授权
    Embedded harmonic termination on high power RF transistor 有权

    公开(公告)号：US09899967B1

    公开(公告)日：2018-02-20

    申请号：US15421567

    申请日：2017-02-01

    Applicant: Infineon Technologies AG

    Inventor： Cristian Gozzi ,  Guillaume Bigny

    IPC: H03F3/04 ,  H03F1/56 ,  H03F3/213 ,  H03F3/195 ,  H01L21/768

    CPC classification number: H01L21/76898 ,  H01L23/528 ,  H01L23/66

    Abstract: A semiconductor includes a semiconductor substrate having first and second opposite facing surfaces. An amplifier device is formed in the semiconductor substrate, the amplifier device is configured to amplify an RF signal at a fundamental frequency. A first dielectric layer is formed on the first surface of the substrate. A first metallization layer is formed on the first dielectric layer. The first metallization layer is spaced apart from the substrate by the first dielectric layer. The first metallization layer includes a first elongated finger interdigitated with a first reference potential pad. The first elongated finger is physically disconnected from the first reference potential pad. The first reference potential pad includes a first patterned shape that is devoid of metallization. The first patterned shape has a geometry that filters harmonic components of the fundamental frequency.

    PCB Based Semiconductor Package Having Integrated Electrical Functionality
    2.
    发明申请
    PCB Based Semiconductor Package Having Integrated Electrical Functionality 有权
    具有集成电气功能的基于PCB的半导体封装

    公开(公告)号：US20170034913A1

    公开(公告)日：2017-02-02

    申请号：US14811325

    申请日：2015-07-28

    Applicant: Infineon Technologies AG

    Inventor： Qianli Mu ,  Cristian Gozzi ,  Michael Simcoe ,  Guillaume Bigny

    IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

    CPC classification number: H05K1/181 ,  H01L23/142 ,  H01L23/64 ,  H01L2224/49175 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/182 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10166 ,  H05K2203/049

    Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

    Abstract translation: 半导体封装包括金属基板，具有附接到基板的参考端子的半导体管芯和远离基板的RF端子，以及多层电路板，其具有附接到基板的第一侧和远离基板的第二侧 底盘。 多层电路板包括多个交错信号和接地层。 信号层中的一个位于多层电路板的第二侧并电连接到半导体管芯的RF端子。 其中一个接地层位于多层电路板的第一侧并附着在金属底板上。 功率分配结构形成在多层电路板的第二侧的信号层中。 RF匹配结构形成在与功率分配结构不同的信号层中。

    MULTI-CAVITY PACKAGE HAVING SINGLE METAL FLANGE
    4.
    发明申请
    MULTI-CAVITY PACKAGE HAVING SINGLE METAL FLANGE 审中-公开
    具有单金属法兰的多孔包装

    公开(公告)号：US20160294340A1

    公开(公告)日：2016-10-06

    申请号：US14673928

    申请日：2015-03-31

    Applicant: Infineon Technologies AG

    Inventor： Saurabh Goel ,  Alexander Komposch ,  Cynthia Blair ,  Cristian Gozzi

    IPC: H03F3/21 ,  H01L23/498 ,  H01L25/16 ,  H03F3/19 ,  H01L25/065 ,  H01L23/66 ,  H01L25/00 ,  H03F1/02 ,  H01L23/495 ,  H01L25/07

    Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

    Abstract translation: 多空腔包装包括具有第一和第二相对主表面的单个金属凸缘，附接到单个金属凸缘的第一主表面的电路板，电路板具有多个开口，其暴露第一主表面的不同区域 的单个金属凸缘，以及多个半导体管芯，每个半导体管芯设置在电路板的一个开口中并且附接到单个金属法兰的第一主表面。 电路板包括用于电连接半导体管芯以形成电路的多个金属迹线。 还提供了相应的制造方法。

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