公开(公告)号：US20240371777A1

公开(公告)日：2024-11-07

申请号：US18141887

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Arijit KOLEY ,  Ashish BHATIA ,  Wayne M. LYTLE ,  Stephen SUDIRGO ,  Nora BERG ,  Patrick WHITING ,  Michael MUSORRAFITI ,  Olawale Taiwo OLADEINDE ,  Emily TIMMINS ,  Beatrice MURIUNGI ,  Matthew TAYLOR

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a via is provided through the substrate, where a portion of the via extends past the second surface. In an embodiment, a first layer is over the substrate, where the first layer is an electrically insulating material. In an embodiment, a second layer is over the first layer and over the portion of the via that extends past the second surface.

公开(公告)号：US20190237391A1

公开(公告)日：2019-08-01

申请号：US16329170

申请日：2016-10-27

Applicant: Intel Corporation

Inventor： Seshu V. SATTIRAJU ,  Krishna Prakash GANESAN ,  Ashish BHATIA ,  Vinay SRIRAM ,  John MUIRHEAD ,  Hiten KOTHARI ,  Aloysius A. GUNAWAN ,  Lavanya ARYASOMAYAJULA ,  Shravan GOWRISHANKAR ,  Sriram PATTABHIRAMAN ,  Sudipto GUHA

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822

CPC classification number: H01L23/481 ,  H01L21/48 ,  H01L21/76876 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/00 ,  H01L23/48 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05657 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/335 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.