公开(公告)号：US20170027062A1

公开(公告)日：2017-01-26

申请号：US15286276

申请日：2016-10-05

Applicant: Intel Corporation

Inventor： MIHIR K. ROY ,  Mathew J. MANUSHAROW

IPC: H05K3/10 ,  H05K3/30 ,  H05K1/16 ,  H05K3/22 ,  H05K3/40

CPC classification number: H05K3/10 ,  H01B3/485 ,  H01B3/50 ,  H01B7/083 ,  H01F17/0006 ,  H05K1/0222 ,  H05K1/038 ,  H05K1/165 ,  H05K3/043 ,  H05K3/103 ,  H05K3/22 ,  H05K3/26 ,  H05K3/30 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/029 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/1081 ,  H05K2203/0228 ,  H05K2203/025 ,  H05K2203/1461 ,  H05K2203/175 ,  H05K2203/30

Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

Abstract translation: 衬底封装包括织造织物，其具有在导电股线之间编织的非导电股线，包括线股，同轴股线和/或股线的电感器图案。 封装可以通过廉价且高通量的工艺来形成，该工艺首先在导电股线之间编织非导电股线（例如玻璃），以形成机织织物中导电股线的电路板图案。 接下来，用树脂材料浸渍织物以形成浸渍织物，然后将其固化以形成固化织物。 随后将固化的织物的上表面和下表面平坦化。 平面化节段并露出导线，同轴和电感图案线的端部。 由于导电丝线整体地形成在平面织造织物内，所以基底具有高的机械稳定性，并提供了在基底包装中原位构建的基于导线的电气部件。

公开(公告)号：US20150089806A1

公开(公告)日：2015-04-02

申请号：US14566208

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： MIHIR K. ROY ,  ISLAM A. SALAMA ,  YONGGANG LI

IPC: H05K3/42 ,  G06F1/18

CPC classification number: H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract translation: 半导体器件基板包括前部和后部，其是设置在第一芯的前表面和后表面上的层叠芯。 第一芯具有圆柱形电镀通孔，其已被金属电镀并填充有空芯材料。 前部和后部具有激光钻孔的锥形通孔，其填充有导电材料并且连接到电镀通孔。 后部包括与前部连通的整体电感线圈。 第一芯和层叠芯形成具有集成电感线圈的混合芯半导体器件衬底。