公开(公告)号：US09805773B1

公开(公告)日：2017-10-31

申请号：US15161908

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J Allen

IPC: H03K5/156 ,  G11C7/10 ,  H03K5/05 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2211/4061 ,  H03K5/05 ,  H03K5/1565

Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

公开(公告)号：US09455726B1

公开(公告)日：2016-09-27

申请号：US14745321

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Michael J Allen ,  Khushal N Chandan ,  Setul M Shah

IPC: H03K3/00 ,  H03K3/64 ,  H03K3/78 ,  H03L7/081 ,  H03K19/21

CPC classification number: H03L7/0814 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K19/21 ,  H03L7/0818

Abstract: Phase compensation in an I/O (input/output) circuit includes a triangular control contour with a simplified generation circuit. A linear control circuit can generate a digital N-bit linear count, and route the least significant M bits [(M−1):0] for linear control for fine delay mixing of a phase compensation loop and the most significant (N−M) bits [(N−1):M] for linear control for coarse control of a delay chain for the phase compensation loop. Prior to decoding the least significant M bits for fine delay mixing, the control circuit performs a bitwise XOR (exclusive OR) of bit M with each of bits [(M−1):0] to generate M linear control bits as the linear control for fine delay mixing. The M linear control bits generate a linear control count having a triangular contour, where the linear control count continuously, repeatedly counts from 0 to (2M−1) to 0.

Abstract translation: I / O（输入/输出）电路中的相位补偿包括具有简化的生成电路的三角形控制轮廓。 线性控制电路可以产生数字N位线性计数，并路由最小有效M位[（M-1）：0]用于线性控制，用于相位补偿环路的精细延迟混合和最高有效位（N-M ）位[（N-1）：M]用于相位补偿回路的延迟链的粗略控制的线性控制。 在对最小有效M位解码以进行精细延迟混合之前，控制电路执行位M与位[（M-1）：0]的按位XOR（异或），以产生M个线性控制位作为线性控制 用于精细延迟混合。 M个线性控制位产生具有三角形轮廓的线性控制计数，其中线性控制计数连续地从0到（2M-1）重复计数到0。

公开(公告)号：US09407273B1

公开(公告)日：2016-08-02

申请号：US14730514

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Michael J Allen

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/08

CPC classification number: H03L7/0814 ,  H03L7/0816

Abstract: A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the feedback signal with a leading edge transition in the reference clock signal. The DLL training circuit further provides an inverted feedback signal to the DLL and receives a second delay code value from the DLL that corresponds to the delay added to the inverted feedback signal to align a leading edge transition in the inverted feedback signal with a leading edge transition in the reference clock signal. The DLL selectively adds the delay code corresponding to the temporally smaller of the first delay code value or the second delay code value to the feedback signal to align the feedback signal with the reference clock signal.

Abstract translation: DLL可以包括DLL训练电路，其向DLL提供反馈信号，并且从DLL中接收对应于添加到反馈信号的延迟的第一延迟码值，以将反馈信号中的前沿转变与前沿 转换参考时钟信号。 DLL训练电路还向DLL提供反向反馈信号，并从DLL中接收对应于反相反馈信号的延迟的第二延迟码值，以将反向反馈信号中的前沿跃迁与前沿转换 在参考时钟信号中。 该DLL选择性地将对应于第一延迟码值或第二延迟码值的时间上较小的延迟码添加到反馈信号，以使反馈信号与参考时钟信号对准。

公开(公告)号：US10381055B2

公开(公告)日：2019-08-13

申请号：US14998185

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Michael J Allen ,  Rajesh Sundaram

IPC: G11C7/22 ,  G11C29/02 ,  G11C29/12 ,  G06F13/16

Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

公开(公告)号：US09614533B2

公开(公告)日：2017-04-04

申请号：US14745326

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Setul M Shah ,  Michael J Allen ,  Khushal N Chandan

IPC: H03L7/087 ,  H03L7/081 ,  G11C7/10

CPC classification number: H03L7/0814 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0818

Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.