公开(公告)号：US09780054B2

公开(公告)日：2017-10-03

申请号：US14529881

申请日：2014-10-31

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H01L21/768 ,  H01L25/07 ,  H01L23/31 ,  H01L25/11 ,  H05K3/46

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

公开(公告)号：US08809124B2

公开(公告)日：2014-08-19

申请号：US13934522

申请日：2013-07-03

Applicant: Intel Corporation

Inventor： Mathew J Manusharow ,  Mark S Hlad ,  Ravi K Nalla

IPC: H01L23/485

CPC classification number: H01L21/50 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/4641 ,  H01L2924/00

Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Abstract translation: 一种结构包括用于支撑半导体器件的混合衬底，该半导体器件包括其中嵌入半导体器件的无凸起积聚层和层叠芯结构。 通过与层压芯结构中的电镀通孔连接的无刷构建层结构的后续接合焊盘的加强电镀将无凸起的堆积层和层叠芯结构作为一体的装置。