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    High density interconnect device and method
    1.
    发明授权
    High density interconnect device and method 有权

    公开(公告)号：US11158578B2

    公开(公告)日：2021-10-26

    申请号：US16601297

    申请日：2019-10-14

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Mathew J Manusharow

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

    High density interconnect device and method
    3.
    发明授权
    High density interconnect device and method 有权

    公开(公告)号：US10446499B2

    公开(公告)日：2019-10-15

    申请号：US15438321

    申请日：2017-02-21

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Mathew J Manusharow

    IPC: H01L23/13 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

    Method of making an inductor
    6.
    发明授权
    Method of making an inductor 有权

    公开(公告)号：US10998120B2

    公开(公告)日：2021-05-04

    申请号：US16162465

    申请日：2018-10-17

    Applicant: Intel Corporation

    Inventor： William J. Lambert ,  Mihir K Roy ,  Mathew J Manusharow ,  Yikang Deng

    IPC: H01F7/06 ,  H01F27/28 ,  H01F17/00 ,  H01F41/04 ,  C25D5/16 ,  C25D5/48 ,  C25D7/00 ,  H01F27/255 ,  H01F41/02

    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

    Inductor formed in substrate
    10.
    发明授权
    Inductor formed in substrate 有权

    公开(公告)号：US10312007B2

    公开(公告)日：2019-06-04

    申请号：US13711149

    申请日：2012-12-11

    Applicant: Intel Corporation

    Inventor： Mihir K Roy ,  Mathew J Manusharow ,  Harold Ryan Chase

    IPC: H01F17/00

    Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.

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