公开(公告)号：US09059156B2

公开(公告)日：2015-06-16

申请号：US14090822

申请日：2013-11-26

Applicant: Intermolecular Inc.

Inventor： Zhendong Hong ,  Ashish Bodke ,  Olov Karlsson

IPC: H01L21/336 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833

Abstract: Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.

Abstract translation: 公开了形成金属栅极晶体管器件的方法。 矽硅化物层可用于CMOS晶体管，其中铒硅化物层的功函数可调谐用于PMOS和NMOS器件。 可以使用Nanoaminate溅射方法，其中交替沉积硅和铒层以确定特定栅极堆叠的最佳层性质，组成分布和铒与硅比。

公开(公告)号：US09006026B2

公开(公告)日：2015-04-14

申请号：US14466695

申请日：2014-08-22

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Zhendong Hong ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Hieu Pham ,  Takeshi Yamaguchi

IPC: H01L21/00 ,  H01L21/8222 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化 ）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。 由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。 在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。

公开(公告)号：US20160093711A1

公开(公告)日：2016-03-31

申请号：US14315079

申请日：2014-06-25

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Zhendong Hong ,  Paul Besser ,  Kisik Choi ,  Amol Joshi ,  Olov Karlsson ,  Susie Tzeng

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

Abstract translation: 具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。 碳化钽（TaC）具有对厚度不敏感的中间间隙功能。 可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。 可以添加Al来调节阈值电压。

公开(公告)号：US09297775B2

公开(公告)日：2016-03-29

申请号：US14285921

申请日：2014-05-23

Applicant: Intermolecular Inc.

Inventor： Edwin Adhiprakasha ,  Sean Barstow ,  Ashish Bodke ,  Zhendong Hong ,  Usha Raghuram ,  Karthik Ramani ,  Vivian Ryan ,  Jingang Su ,  Xunyuan Zhang

IPC: H01L27/20 ,  G01N27/20 ,  C23C14/34 ,  C23C14/54 ,  C23C14/06 ,  G01N27/04

CPC classification number: G01N27/20 ,  C23C14/06 ,  C23C14/14 ,  C23C14/3464 ,  C23C14/54 ,  C23C14/548 ,  G01N27/041

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

公开(公告)号：US20150338362A1

公开(公告)日：2015-11-26

申请号：US14285921

申请日：2014-05-23

Applicant: Intermolecular Inc.

Inventor： Edwin Adhiprakasha ,  Sean Barstow ,  Ashish Bodke ,  Zhendong Hong ,  Usha Raghuram ,  Karthik Ramani ,  Vivian Ryan ,  Jingang Su ,  Xunyuan Zhang

IPC: G01N27/20 ,  G01N27/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/54

CPC classification number: G01N27/20 ,  C23C14/06 ,  C23C14/14 ,  C23C14/3464 ,  C23C14/54 ,  C23C14/548 ,  G01N27/041

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract translation: 使用通过不同大小的孔溅射或共溅射的测试结构组合地筛选用于小规模互连（例如铜）的阻挡层，阻挡层和种子层。 在退火之前和/或之后测量与导电性，扩散阻挡和粘附有关的各种特性（例如，电阻率，结晶形态，表面粗糙度）并进行比较以获得材料和工艺参数，以通过互连实现高导电性的低扩散。 示例结果表明，一些钽 - 钛屏障的配方可以替代较厚的钽/氮化钽叠层，在某些情况下可以在Ta-Ti和铜之间具有Cu-Mn种子层。

公开(公告)号：US20160181380A1

公开(公告)日：2016-06-23

申请号：US14576597

申请日：2014-12-19

Applicant: Intermolecular Inc. ,  Global Foundries, Inc.

Inventor： Amol Joshi ,  Sean Barstow ,  Paul Besser ,  Ashish Bodke ,  Guillaume Bouche ,  Nobumichi Fuchigami ,  Zhendong Hong ,  Shaoming Koh ,  Albert Sanghyup Lee ,  Salil Mujumdar ,  Abhijit Pethe ,  Mark Victor Raymond

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/28568 ,  H01L21/02186 ,  H01L21/02362 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/76843 ,  H01L29/47 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839

Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.

Abstract translation: 本文提供的实施例描述了用于形成半导体器件的系统和方法。 提供半导体衬底。 源极区和漏极区形成在半导体衬底上。 在源极区域和漏极区域之间形成栅电极。 在源极区域和漏极区域中的至少一个上方形成接触。 触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。 界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。

公开(公告)号：US20150179935A1

公开(公告)日：2015-06-25

申请号：US14624295

申请日：2015-02-17

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Zhendong Hong ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Hieu Pham ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化 ）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。 由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。 在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。

公开(公告)号：US20150025670A1

公开(公告)日：2015-01-22

申请号：US14505184

申请日：2014-10-02

Applicant: Intermolecular, Inc.

Inventor： Jeremy Cheng ,  Indranil De ,  Ho Yin Owen Fong ,  Zhendong Hong ,  Dan Wang

IPC: G05B19/402

CPC classification number: G05B19/402 ,  B01J19/0046 ,  B01J2219/00326 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00536 ,  B01J2219/00612 ,  B01J2219/00689 ,  B01J2219/00693 ,  B01J2219/00695 ,  C23C14/042 ,  C23C14/505 ,  C23C14/54 ,  G05B2219/45031

Abstract: Substrate processing including correction for deposition location is described, including a combinatorial processing chamber that incorporates the correction. The combinatorial processing chamber can be used to process multiple regions of a substrate using different processing parameters on different regions. For example, one region can have one material deposited on it and another region can have a different material deposited on it, although other combinations and variations are possible. The combinatorial processing chamber uses a rotating and revolving substrate pedestal to be able to deposit on all locations or positions on a substrate. The combinatorial processing chamber uses a correction factor that accounts for variations in alignment and/or configuration of the processing chamber so that the actual location of deposition of a region is approximately the same as a desired location of deposition.

Abstract translation: 描述包括用于沉积位置的校正的衬底处理，包括结合了校正的组合处理室。 组合处理室可用于在不同区域上使用不同的处理参数处理衬底的多个区域。 例如，一个区域可以具有沉积在其上的一个材料，而另一个区域可以具有沉积在其上的不同材料，尽管其它组合和变化是可能的。 组合处理室使用旋转和旋转的基板基座能够沉积在基板上的所有位置或位置上。 组合处理室使用考虑处理室的对准和/或配置变化的校正因子，使得区域的实际沉积位置与期望的沉积位置大致相同。

公开(公告)号：US20140363942A1

公开(公告)日：2014-12-11

申请号：US13915324

申请日：2013-06-11

Applicant: Intermolecular Inc.

Inventor： Zhendong Hong ,  Ashish Bodke ,  Susie Tzeng

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28097 ,  H01L21/324 ,  H01L29/4975 ,  H01L29/66795 ,  H01L29/785

Abstract: Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon.

Abstract translation: 硅化钨层可用于CMOS晶体管，其中硅化钨层的功函数可调谐用于PMOS和NMOS器件。 可以使用共溅射方法，其中硅和钨沉积在高介电常数栅极电介质层上。 硅化钨层可以在临界温度以上或高于临界温度退火，以优化硅化钨层的电阻率。 在一些实施例中，沉积的硅化钨的浓度可以在50at％的硅与80at％的硅之间。 较高的硅浓度，例如700℃，63at％硅至600℃，74at％的硅，临界温度可以较低。

公开(公告)号：US20140363920A1

公开(公告)日：2014-12-11

申请号：US14466695

申请日：2014-08-22

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Zhendong Hong ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Hieu Pham ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化 ）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。 由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。 在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。