公开(公告)号：US08759212B2

公开(公告)日：2014-06-24

申请号：US13101569

申请日：2011-05-05

申请人： Ippei Kume ,  Jun Kawahara ,  Naoya Furutake ,  Shinobu Saitou ,  Yoshihiro Hayashi

发明人： Ippei Kume ,  Jun Kawahara ,  Naoya Furutake ,  Shinobu Saitou ,  Yoshihiro Hayashi

IPC分类号： H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.

摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成包括Si和C的帽绝缘膜; 在盖绝缘膜上形成具有碳原子数与硅原子数相比高于盖绝缘膜的组成比的有机二氧化硅膜; 在有机二氧化硅膜中形成具有不同开口直径的两个以上的凹部，通过使用包含惰性气体，含N气体，碳氟化合物气体和氧化剂气体的混合气体的等离子体处理。

公开(公告)号：US20100123199A1

公开(公告)日：2010-05-20

申请号：US12591089

申请日：2009-11-06

申请人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

发明人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.

摘要翻译： 提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极 电极和连接到上电极的上电容器布线。

公开(公告)号：US08390046B2

公开(公告)日：2013-03-05

申请号：US12947254

申请日：2010-11-16

申请人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

发明人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

IPC分类号： H01L29/772

CPC分类号： H01L23/53238 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.

摘要翻译： 本发明的半导体器件具有形成在其上的晶体管的半导体衬底; 形成在半导体衬底上的多层互连，并且具有分别由互连和绝缘膜组成的多个互连层，堆叠在其中; 以及具有下部电极（下部电极膜），电容器绝缘膜和上部电极（上部电极膜）的电容元件，其全部嵌入在多层互连件中，以构成存储元件，以及 还包括形成在电容元件和晶体管之间的至少一层镶嵌结构的铜互连（第二层互连）; 一个互连（第二层互连）和电容元件的下表面的上表面几乎在同一平面内排列; 并且在电容元件上形成至少一层铜互连（板线互连）。

公开(公告)号：US20090309186A1

公开(公告)日：2009-12-17

申请号：US12519706

申请日：2007-12-25

申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US08629529B2

公开(公告)日：2014-01-14

申请号：US12519706

申请日：2007-12-25

申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L27/06

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

公开(公告)号：US08624328B2

公开(公告)日：2014-01-07

申请号：US12591089

申请日：2009-11-06

申请人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

发明人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.

摘要翻译： 提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极 电极和连接到上电极的上电容器布线。

公开(公告)号：US20110284991A1

公开(公告)日：2011-11-24

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US06541396B2

公开(公告)日：2003-04-01

申请号：US09983378

申请日：2001-10-24

申请人： Jun Kawahara ,  Yoshihiro Hayashi

发明人： Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a method for manufacturing a semiconductor device having a first insulation film, a second insulation film formed over the first insulation film, an inlaid interconnection formed in the second insulation film, and an organic film provided on the inlaid interconnection layer and the second insulation film, the organic film having a dielectric constant lower than the second insulation film, the organic film is grown inside a vacuum chamber.

摘要翻译： 在制造具有第一绝缘膜的半导体器件的方法中，形成在第一绝缘膜上的第二绝缘膜，形成在第二绝缘膜中的嵌入互连以及设置在镶嵌互连层上的有机膜和第二绝缘膜 有机膜的介电常数低于第二绝缘膜，有机膜在真空室内生长。

公开(公告)号：US6100201A

公开(公告)日：2000-08-08

申请号：US33912

申请日：1998-03-03

申请人： Yukihiko Maejima ,  Jun Kawahara ,  Shinobu Saitoh ,  Yoshihiro Hayashi

发明人： Yukihiko Maejima ,  Jun Kawahara ,  Shinobu Saitoh ,  Yoshihiro Hayashi

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L21/461

CPC分类号： H01L28/55 ,  H01L21/3105 ,  H01L21/31122

摘要： A method of forming a capacitor by forming a dielectric layer over a bottom electrode layer, forming a top electrode layer over the dielectric layer to form laminations of the bottom electrode layer, the dielectric layer and the top electrode layer, and selectively etching the laminations to form a capacitor, the dielectric layer being etched by a reactive ion etching so that the dielectric layer of the capacitor receives no substantive damage in the etching process.

摘要翻译： 一种通过在底部电极层上形成电介质层形成电容器的方法，在电介质层上形成顶部电极层以形成底部电极层，电介质层和顶部电极层的叠层，并选择性地蚀刻叠片至 形成电容器，通过反应离子蚀刻蚀刻电介质层，使得电容器的电介质层在蚀刻工艺中不会受到实质的损坏。