公开(公告)号：US08552564B2

公开(公告)日：2013-10-08

申请号：US12964457

申请日：2010-12-09

申请人： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

发明人： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

IPC分类号： H01L23/48

CPC分类号： H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

摘要翻译： 半导体器件基板包括前部和后部，其是设置在第一芯的前表面和后表面上的层叠芯。 第一芯具有圆柱形电镀通孔，其已被金属电镀并填充有空芯材料。 前部和后部具有激光钻孔的锥形通孔，其填充有导电材料并且连接到电镀通孔。 后部包括与前部连通的整体电感线圈。 第一芯和层叠芯形成具有集成电感线圈的混合芯半导体器件衬底。

公开(公告)号：US08183496B2

公开(公告)日：2012-05-22

申请号：US12319016

申请日：2008-12-30

申请人： Yonggang Li ,  Islam Salama

发明人： Yonggang Li ,  Islam Salama

IPC分类号： B23K26/36

CPC分类号： B23K26/082 ,  B23K26/066 ,  B23K26/361 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  Y10T29/49155 ,  Y10T428/24306

摘要： A method of forming a pattern (700) on a work piece (1260) includes placing a pattern mask (1210) over the work piece, placing an aperture (100, 500, 600, 1220) over the pattern mask, and placing the work piece in a beam of electromagnetic radiation (1240). The aperture includes three adjacent sections. A first section (310) has a first side (311), a second side (312), and a first length (313). A second section (320) has a third side (321) adjacent to the second side, a fourth side (322), a second length (323), and a first width (324). A third section (330) has a fifth side (331) adjacent to the fourth side, a sixth side (332), and a third length (333). The first and third lengths are substantially equal. The first and third sections are complementary shapes, as defined herein.

摘要翻译： 在工件（1260）上形成图案（700）的方法包括将图案掩模（1210）放置在工件上方，在图案掩模上放置孔（100,500,600,1220），并将工件 在电磁辐射束（1240）中。 光圈包括三个相邻的部分。 第一部分（310）具有第一侧（311），第二侧（312）和第一长度（313）。 第二部分（320）具有与第二侧相邻的第三侧（321），第四侧（322），第二长度（323）和第一宽度（324）。 第三部分（330）具有与第四侧相邻的第五侧（331），第六侧（332）和第三长度（333）。 第一和第三长度基本相等。 第一和第三部分是如本文所定义的互补形状。

公开(公告)号：US20100126009A1

公开(公告)日：2010-05-27

申请号：US12315066

申请日：2008-11-25

申请人： Yonggang Li ,  Islam Salama

发明人： Yonggang Li ,  Islam Salama

IPC分类号： H05K3/42

CPC分类号： H05K3/107 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/108 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.

摘要翻译： 在衬底（201）上进行选择性区域电镀的方法包括在衬底上形成第一导电层（310），用抗化学镀层（410）覆盖导电层，图案化衬底以形成 其中延伸穿过抗化学镀层和第一导电层的特征（510,520），形成邻接并电连接到第一导电层的第二导电层（610），形成第三导电层（ 710），并且去除所述防电镀层和所述第一导电层。

公开(公告)号：US09648733B2

公开(公告)日：2017-05-09

申请号：US13861338

申请日：2013-04-11

申请人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H05K1/02 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/426 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

公开(公告)号：US08288682B2

公开(公告)日：2012-10-16

申请号：US11863895

申请日：2007-09-28

申请人： Islam Salama ,  Yonggang Li

发明人： Islam Salama ,  Yonggang Li

IPC分类号： B23K26/38

CPC分类号： H05K3/0035 ,  H05K1/116 ,  H05K3/107 ,  H05K2201/09845 ,  H05K2203/108

摘要： A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via.

摘要翻译： 公开了一种在衬底上形成至少一个微通孔的方法。 该方法包括通过使用第一激光束在衬底中钻取至少一个孔。 第一激光束具有在第一激光束的边缘处比在第一激光束的中心更多的能量分布。 该方法还包括通过使用第二激光束去除衬底的至少一部分，在衬底的顶表面上并围绕至少一个孔的外周形成至少一个坯料图案。 多个空白图案中的至少一个空白图案对应于至少一个微孔的垫。 此后，该方法包括用导电材料填充多个坯料图案和至少一个微通孔，以形成至少微通孔。

公开(公告)号：US20120146180A1

公开(公告)日：2012-06-14

申请号：US12964457

申请日：2010-12-09

申请人： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

发明人： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

IPC分类号： H01L23/528 ,  H01L29/40 ,  H01L21/44

CPC分类号： H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

摘要翻译： 半导体器件基板包括前部和后部，其是设置在第一芯的前表面和后表面上的层叠芯。 第一芯具有圆柱形电镀通孔，其已被金属电镀并填充有空芯材料。 前部和后部具有激光钻孔的锥形通孔，其填充有导电材料并且连接到电镀通孔。 后部包括与前部连通的整体电感线圈。 第一芯和层叠芯形成具有集成电感线圈的混合芯半导体器件衬底。

公开(公告)号：US07891091B2

公开(公告)日：2011-02-22

申请号：US12315066

申请日：2008-11-25

申请人： Yonggang Li ,  Islam Salama

发明人： Yonggang Li ,  Islam Salama

IPC分类号： H01K3/10

CPC分类号： H05K3/107 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/108 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.

摘要翻译： 在衬底（201）上进行选择性区域电镀的方法包括在衬底上形成第一导电层（310），用抗化学镀层（410）覆盖导电层，图案化衬底以形成 其中延伸穿过抗化学镀层和第一导电层的特征（510,520），形成邻接并电连接到第一导电层的第二导电层（610），形成第三导电层（ 710），并且去除所述防电镀层和所述第一导电层。

公开(公告)号：US20090002958A1

公开(公告)日：2009-01-01

申请号：US11769900

申请日：2007-06-28

申请人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H05K1/02 ,  H05K3/00

CPC分类号： H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/426 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

摘要翻译： 制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二补充图案化导电层提供到第一和第二辅助绝缘层的相应的一个上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层 其中。

公开(公告)号：US08440916B2

公开(公告)日：2013-05-14

申请号：US11769900

申请日：2007-06-28

申请人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H05K1/11

CPC分类号： H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/426 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

摘要翻译： 制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二补充图案化导电层提供到第一和第二辅助绝缘层的相应的一个上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层 其中。

公开(公告)号：US20090001550A1

公开(公告)日：2009-01-01

申请号：US11769852

申请日：2007-06-28

申请人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy

发明人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy

IPC分类号： H01L23/14 ,  H05K1/02 ,  H05K3/42

CPC分类号： H05K3/422 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49128 ,  Y10T29/49165

摘要： A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

摘要翻译： 一种制造衬底芯结构的方法，以及根据该方法形成的衬底芯结构。 该方法包括：通过起始绝缘层激光钻探第一组通路孔; 用导电材料填充第一组通孔开口以提供第一组导电通孔; 在起始绝缘层的相对侧上提供第一和第二图案化导电层; 在所述第一图案化导电层上提供补充绝缘层; 激光钻穿通过补充绝缘层的第二组通孔; 用导电材料填充第二组通孔开口以提供第二组导电通路; 以及在所述补充绝缘层的暴露侧上提供补充图案化导电层，所述第二组导电通孔在其相对侧与所述第一图案化导电层和所述补充图案化导电层接触。