公开(公告)号：US20140207396A1

公开(公告)日：2014-07-24

申请号：US13544080

申请日：2012-07-09

申请人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

发明人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC分类号： G01R31/28

CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

摘要： Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

摘要翻译： 用于可靠性测试的系统包括配置成测量被测器件（DUT）上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统，以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置， 在时间上对应于增加的光发射的情况。

公开(公告)号：US09557369B2

公开(公告)日：2017-01-31

申请号：US13530782

申请日：2012-06-22

申请人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

发明人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC分类号： G01R31/28 ,  G01R31/311

CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

摘要： Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

摘要翻译： 可靠性测试方法包括对被测设备（DUT）施加应力电压; 测量穿过DUT的漏电流; 基于泄漏电流测量的定时，触发DUT测量光发射; 并且将泄漏电流的测量与光发射的测量值相关联，以通过将泄漏电流中增加的噪声的实例定位在与增加的光发射的情况相对应的时间内来确定DUT内的缺陷发生的时间和位置。

公开(公告)号：US09448277B2

公开(公告)日：2016-09-20

申请号：US13544080

申请日：2012-07-09

申请人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

发明人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC分类号： G01R31/28 ,  G01R31/311

CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

摘要： Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

摘要翻译： 用于可靠性测试的系统包括配置成测量被测器件（DUT）上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统，以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置， 在时间上对应于增加的光发射的情况。

公开(公告)号：US20130345997A1

公开(公告)日：2013-12-26

申请号：US13530782

申请日：2012-06-22

申请人： JIFENG CHEN ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

发明人： JIFENG CHEN ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC分类号： G01R31/12 ,  G06F19/00

CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

摘要： Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

摘要翻译： 可靠性测试方法包括对被测设备（DUT）施加应力电压; 测量穿过DUT的漏电流; 基于泄漏电流测量的定时，触发DUT测量光发射; 并且将泄漏电流的测量与光发射的测量值相关联，以通过将泄漏电流中增加的噪声的实例定位在与增加的光发射的情况相对应的时间内来确定DUT内的缺陷发生的时间和位置。

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US20130049207A1

公开(公告)日：2013-02-28

申请号：US13221698

申请日：2011-08-30

申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

IPC分类号： H01L21/26 ,  H01L23/485 ,  H01L21/66

CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US08076756B2

公开(公告)日：2011-12-13

申请号：US13031195

申请日：2011-02-19

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L23/544

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US07973409B2

公开(公告)日：2011-07-05

申请号：US11625576

申请日：2007-01-22

申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

公开(公告)号：US20100295181A1

公开(公告)日：2010-11-25

申请号：US12468478

申请日：2009-05-19

申请人： Chih-Chao Yang ,  Thomas M. Shaw

发明人： Chih-Chao Yang ,  Thomas M. Shaw

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.

摘要翻译： 为互连结构提供冗余金属扩散屏障，从而提高互连结构的可靠性和可扩展性。 冗余金属扩散阻挡层位于位于电介质材料内的开口内，并且位于扩散阻挡层和也存在于开口内的导电材料之间。 冗余扩散阻挡层包括单层或多层结构，其包含Ru和包含纯Co或Co合金的含Co材料，其包括N，B和P中的至少一种。